Methods for fabricating cmos integrated circuits having metal silicide contacts
AssigneeGlobalfoundries Inc.
InventorsStefan FLACHOWSKY, Ralf ILLGEN, Ina OSTERMAY, Jan HOENTSCHEL
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Abstract
Methods are provided for fabricating CMOS integrated circuits. In accordance with one embodiment the methods include forming a gate electrode structure overlying an N-doped portion of a semiconductor substrate and growing an embedded silicon germanium area in the N-doped portion in alignment with the gate electrode structure. A layer of silicon is selectively grown overlying the embedded silicon germanium area and a nickel silicide contact is made to the layer of silicon.
Claims20
A method for fabricating a CMOS integrated circuit comprising:
- forming a gate electrode structure overlying an N-doped portion of a semiconductor substrate;
- growing an embedded silicon germanium area in the N-doped portion in alignment with the gate electrode structure;
- selectively growing a layer of silicon overlying the embedded silicon germanium area;
- and
- forming a nickel silicide contact to the layer of silicon.
A method for fabricating a CMOS integrated circuit comprising:
- forming a P-type region and an N-type region in a silicon substrate;
- forming a first gate electrode structure overlying the P-type region and a second gate electrode structure overlying the N-type region;
- etching a recess in the N-type region in alignment with the second gate electrode structure;
- growing embedded silicon germanium in the recess;
- ion implanting N-type source and drain regions in the P-type region in alignment with the first gate electrode structure and P-type source and drain regions in the N-type region in and through the embedded silicon germanium in alignment with the second gate electrode structure;
- growing a silicon layer overlying the P-type source and drain regions;
- depositing a layer comprising nickel to form nickel silicide contacts to the N-type source and drain regions and to the P-type source and drain regions;
- forming a tensile insulating layer overlying the P-type region and a compressive insulating layer overlying the N-type region;
- and
- forming metallic contacts to the nickel silicide contacts.
A method for fabricating a CMOS integrated circuit comprising:
- etching a recess extending into a silicon substrate;
- filling the recess with silicon germanium grown by a process of selective epitaxial growth;
- growing a layer of silicon overlying the silicon germanium by a process of selective epitaxial growth;
- depositing a layer comprising a silicide forming metal overlying the layer of silicon;
- heating the layer comprising a silicide forming metal to react the metal with the layer of silicon to form a metal silicide, the metal silicide having a thickness to consume substantially all of the layer of silicon;
- depositing a layer of tensile insulating material overlying the metal silicide and heating the layer of tensile insulating material;
- removing a portion of the layer of tensile insulating material and depositing a layer of compressive insulating material;
- and
- forming metallic contacts to the metal silicide.
Dependencies are inferred from the claim text.