Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

A test structure for obtaining electrical measurement data,

• said test structure comprising:
• a first test region comprising:
• a semiconductor layer formed above a substrate;
• a first cavity formed adjacent to and offset from a gate electrode structure formed above said semiconductor layer;
• a second cavity formed adjacent to and offset from said gate electrode structure at a side opposite to said first cavity;
• and
• a first contact structure configured to enable access by an electrical test equipment, said first contact structure being configured to enable a current flow through a bottom portion of said first and second cavities, said first contact structure comprising at least a first contact element and a second contact element defining a predetermined first lateral distance between each other;
• said test structure further comprising:
• a first reference region comprising:
• a reference contact structure connecting to a non-recessed portion of said semiconductor layer, said reference contact structure configured to enable access by said electrical test equipment, said reference contact structure comprising at least a first reference contact element and a second reference contact element defining a second lateral distance between each other, said first and second lateral distances having a predefined correlation to each other.