Thin film transistor display panel and manufacturing method thereof

A method for manufacturing a thin film transistor array panel, comprising:

• forming a gate electrode on a substrate;
• forming a gate insulating layer on the gate electrode;
• forming a semiconductor on the gate insulating layer;
• forming a source electrode and a drain electrode on the semiconductor, the source electrode and drain electrode being spaced apart from each other;
• forming a first passivation layer comprising silicon oxide between the source electrode and the drain electrode;
• forming a second passivation layer comprising silicon nitride on the source electrode, the drain electrode, and the first passivation layer;
• and
• forming a pixel electrode connected to the drain electrode.

A thin film transistor, comprising:

• a gate electrode;
• a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer;
• an insulating layer disposed between the gate electrode and the source and drain electrodes;
• a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor;
• a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes;
• and
• a second passivation layer disposed on the upper layer of the source and drain electrodes.