# US 2012/0223047 A1 · Method of forming multilayer capacitors in a printed circuit substrate

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- Number: US 2012/0223047 A1
- Document ID: US20120223047A1
- Status: Published application
- Kind: A1
- Application number: 12/909,983
- Filed: 2010-10-22
- Published: 2012-09-06
- Earliest claimed: 2005-01-10
- Assignees: Endicott Interconnect Technologies, Inc.
- Inventors: Rabindra N. Das; Frank D. Egitto; How T. Lin; John M. Lauffer; Voya R. Markovich
- Web page: https://patentgrep.com/patent/US20120223047A1

## CPC

- H01G 4/206: {inorganic and synthetic material}
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H05K 1/162: {incorporating printed capacitors}
- H05K 3/06: the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)}
- H05K 3/125: {by ink-jet printing}
- H05K 3/18: using precipitation techniques to apply the conductive material
- H05K 2201/0187: with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
- H05K 2201/0209: Inorganic, non-metallic particles
- H05K 2201/0257: Nanoparticles
- H05K 2201/09309: Core having two or more power planes; Capacitive laminate of two power planes
- Y10T 156/10: Methods of surface bonding and/or assembly therefor
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

## Claims

### Claim 1

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:
a) providing a photoimageable dielectric sheet;
b) providing a planar dielectric substrate having a major surface comprising a predetermined pattern of electrically conductive material thereupon;
c) laminating said photoimageable dielectric sheet to said major surface;
d) exposing and developing said photoimageable dielectric sheet to expose at least a portion of said predetermined pattern of electrically conductive material; and
e) dispensing a capacitor-forming material into an exposed space in said pattern of electrically conductive material, substantially filling said exposed space.

### Claim 2 (depends on 1)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 1, the steps further comprising:
f) curing said capacitor-forming material.

### Claim 3 (depends on 1)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 1, the steps further comprising:
f) at least one of the sub-steps: laminating a planar electrically conductive sheet over said filled exposed space in electrical contact with said electrically conductive pattern; and depositing an electrically conductive layer over said filled exposed space in electrical contact with said electrically conductive pattern.

### Claim 4 (depends on 3)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 3, the steps further comprising:
g) etching a pattern of traces in said at least one of said electrically conductive sheet and said deposited electrically conductive layer.

### Claim 5

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:
a) providing a copper-clad dielectric substrate;
b) etching a pattern of electrically conductive traces in a copper surface of said copper-clad dielectric substrate;
c) laminating a photoimageable dielectric sheet over said electrically conductive traces;
d) exposing and developing said photoimageable dielectric sheet to expose at least a portion of said electrically conductive traces;
e) plating additional copper onto said electrically conductive traces; and
f) dispensing a capacitor-forming material into an exposed space in aid electrically conductive trace, substantially filling said exposed space.

### Claim 6 (depends on 5)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 5, the steps further comprising:
g) curing said capacitor-forming material.

### Claim 7 (depends on 5)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 5, the steps further comprising:
g) at least one of the sub-steps: laminating a planar copper sheet over aid filled exposed space in electrical contact with said electrically conductive pattern;
and depositing a copper layer over said filled exposed space in electrical contact with said electrically conductive pattern.

### Claim 8 (depends on 7)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 7, the steps further comprising:
g) etching a pattern of traces in said at least one of said copper sheet and said deposited copper layer.

### Claim 9

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:
a) providing a dielectric substrate having a predetermined thickness;
b) forming a trench having a predetermined depth in a first major surface of said dielectric substrate;
c) depositing a pattern of electrically conductive traces on a lower surface of said trench, said pattern of electrically conductive traces having a thickness substantially equal to said predetermined trench depth; and
d) dispensing a capacitor-forming material into an exposed space in said pattern of electrically conductive material, substantially filling said exposed space.

### Claim 10 (depends on 9)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 9, the steps further comprising:
e) curing said capacitor-forming material.

### Claim 11 (depends on 9)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 9, the steps further comprising:
e) at least one of the sub-steps: laminating a planar copper sheet over said filled exposed space in electrical contact with said electrically conductive pattern; and depositing a copper layer over said filled exposed space in electrical contact with said electrically conductive traces.

### Claim 12 (depends on 11)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 11, the steps further comprising:
f) etching a pattern of traces in said at least one of said copper sheet and said deposited copper layer.

### Claim 13

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:
a) providing a dielectric substrate having a predetermined thickness;
b) forming a trench having a predetermined depth in a first major surface of said dielectric substrate;
c) depositing a pattern of electrically conductive traces on a lower surface of said trench, said pattern of electrically conductive traces having a thickness less than said predetermined trench depth;
d) plating additional copper onto said electrically conductive traces; and
e) dispensing a capacitor-forming material into an exposed space in said pattern of electrically conductive material, substantially filling said exposed space.

### Claim 14 (depends on 13)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 13, the steps further comprising:
f) curing said capacitor-forming material.

### Claim 15 (depends on 13)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 13, the steps further comprising:
f) at least one of the sub-steps: laminating a planar copper sheet over aid filled exposed space in electrical contact with said electrically conductive pattern; and depositing a copper layer over said filled exposed space in electrical contact with said electrically conductive traces.

### Claim 16 (depends on 15)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 15, the steps further comprising:
g) etching a pattern of traces in said at least one of said copper sheet and said deposited copper layer.

### Claim 17

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:
a) providing a dielectric substrate having a pattern of electrical conductors on a major surface thereof and a photoimageable dielectric laminated to said major surface;
b) developing said photoimageable dielectric to expose at least a portion of said pattern of electrical conductors;
c) plating copper onto said exposed portion of said pattern of electrical conductors to a thickness such that the upper surface of said plated copper is substantially coplanar with a top surface of a remaining portion of said photoimageable dielectric; and
d) dispensing a capacitor-forming material into an exposed space in said pattern of electrical conductors, substantially filling said exposed space.

### Claim 18 (depends on 17)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 17, the steps further comprising:
e) curing said capacitor-forming material.

### Claim 19 (depends on 17)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 17, the steps further comprising:
e) at least one of the sub-steps: laminating a planar copper sheet over said filled exposed space in electrical contact with said electrically conductive pattern; and depositing a copper layer over said filled exposed space in electrical contact with said electrically conductive traces.

### Claim 20 (depends on 19)

The method of forming a multilayer capacitor within a laminated circuit packaging structure as recited in claim 19, the steps further comprising:
f) etching a pattern of traces in said at least one of said copper sheet and said deposited copper layer.