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US 2012/0198194 A1Published application
Multi-Bank Memory Accesses Using Posted Writes
AssigneeRound Rock Research, LLC
InventorJ. Thomas Pawlowski
Life of this patent
Estimating the term…
Abstract
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.
Claims3
A computer system comprising:
- a central processing unit coupled to and configured to communicate with a memory controller by at least an address bus and a data bus, wherein the memory controller is further coupled to one or more memory devices, wherein the memory controller introduces a delay between outputting a memory address for a write access and outputting data for said write access, said delay substantially equal to a period of time between outputting a memory address for a read access and receipt of data corresponding to said read access;
- the memory controller also removing said delay between said memory address for said write access and said data for said write access after receipt of said memory address for said write access and said data for said write access;
- the memory controller transferring said memory address for said write access to one or more said memory device and transferring said data for said write access to one or more said memory devices.
A computer system comprising:
- a central processing unit means in communication with a controller means via an address bus and a data bus;
- the controller means having a means for receiving data and an address for a write access from the address bus and the data bus;
- the controller means in communication with a memory device via the address bus and the data bus, the controller further comprising:
- means for adding delay between said address and said data of said write access such that said added delay is about equal to a delay between receipt of an address of a read access and providing of data corresponding to said address of said read access;
- and
- means for transmitting said write access with said added delay.
3 more elements
An computer system comprising:
- a central processing unit means in communication with a controller means via an address bus and a data bus;
- the controller in communication with a memory device via the address bus and the data bus, the controller comprising:
- means for receiving data and an address for a write access from the address bus and the data bus;
- means for adding delay between an address and data of a write access such that said added delay is about equal to a delay between receipt of an address of a read access and providing of data corresponding to said address of said read access;
- means for transmitting said write access with said added delay to said memory device;
- and
- means for removing said added delay at the memory device.
4 more elements
Dependencies are inferred from the claim text.