Clock divider circuit
AssigneeTexas Instruments Incorporated
InventorRajesh VELAYUTHAN
Life of this patent
Estimating the term…
Abstract
A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2 π/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2 πK/m phase offset from the previous clock output signal.
Claims25
A clock divider that receives m input clock signals each of the same frequency, each input clock signal after the first having a phase offset of 2 π/m, with 2π radians being the phase change in one period of the clock, from the previous input clock signal, and divides the frequency of the input clock signals by an integer of division K, the divider comprising:
- a counter that receives the first input clock signal and provides one or more count signals;
- and
- m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal, and each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2 πK/m phase offset from the previous clock output signal, each flip-flop having a D input that receives a D-input signal comprising one of (1) a count signal and (2) a clock output signal from one of the other flip-flops.
A divide-by-two clock divider that receives eight input clock signals each of the same frequency, a second one of the input clock signals having a phase offset of π/4 from the first one, a third one of the input clock signals having a phase offset of π/4 from the second one, and so on, the divider comprising:
- a one-bit counter that receives the first input clock signal as its clock input;
- a first flip-flop that receives the first input clock signal as its clock input and a zero-count signal from the counter as its D input and provides a first clock output having one-half the frequency of, and the same phase as, the first input clock signal;
- a second flip-flop that receives the third input clock signal as its clock input and the first clock output as its D input and provides a second clock output having the same frequency as, and a phase offset of π/2 from, the first clock output;
- a third flip-flop that receives the fifth input clock signal as its clock input and the first clock output as its D input and provides a third clock output having the same frequency as, and a phase offset of π from, the first clock output;
- a fourth flip-flop that receives the seventh input clock signal as its clock input and the first clock output as its D input and provides a fourth clock output having the same frequency as, and a phase offset of 3 π/2 from, the first clock output;
- a fifth flip-flop that receives the first input clock signal as its clock input and a one-count signal from the counter as its D input and provides a fifth clock output having the same frequency as, and a phase offset of 2π from, the first clock output;
- a sixth flip-flop that receives the third input clock signal as its clock input and the fifth clock output as its D input and provides a sixth clock output having the same frequency as, and a phase offset of 5 π/2 from, the first clock output;
- a seventh flip-flop that receives the fifth input clock signal as its clock input and the fifth clock output as its D input and provides a seventh clock output having the same frequency as, and a phase offset of 3π from, the first clock output;
- and
- an eighth flip-flop that receives the seventh input clock signal as its clock input and the fifth divided output as its D input and provides an eighth clock output having the same frequency as, and a phase offset of 7 π/2 from, the first clock output.
A divide-by-three clock divider that receives eight input clock signals each of the same frequency, each input clock signal after the first having a phase offset of π/4 from the previous input clock signal, the divider comprising:
- a counter that receives the first input clock signal;
- a first flip-flop that receives the first input clock signal as its clock input and a zero-count signal from the counter as its D input and provides a first clock output;
- a second flip-flop that receives the fourth input clock signal as its clock input and the first clock output as its D input and provides a second clock output;
- a third flip-flop that receives the seventh input clock signal as its clock input and the first clock output as its D input and provides a third clock output;
- a fourth flip-flop that receives the second input clock signal as its clock input and a two-count signal from the counter as its D input and provides a fourth clock output;
- a fifth flip-flop that receives the fifth input clock signal as its clock input and the fourth clock output as its D input and provides a fifth clock output;
- a sixth flip-flop that receives the eighth input clock signal as its clock input and the fourth clock output as its D input and provides a sixth clock output;
- a seventh flip-flop that receives the third input clock signal as its clock input and the fourth clock output as its D input and provides a seventh clock output;
- and
- an eighth flip-flop that receives the sixth input clock signal as its clock input and the seventh clock output as its D input and provides an eighth clock output, each clock output after the first having a phase offset of π/4 from the previous clock output.
A divide-by-three clock divider that receives eight input clock signals each of the same frequency, each clock signal after the first having a phase offset of π/4 from the previous clock signal, the divider comprising:
- a counter that receives the first input clock signal;
- a first flip-flop that receives the first input clock signal as its clock input and a sixth clock output as its D input and provides a first clock output;
- a second flip-flop that receives the fourth input clock signal as its clock input and a one-count signal from the counter as its D input and provides a second clock output;
- a third flip-flop that receives the seventh input clock signal as its clock input and the second clock output as its D input and provides a third clock output;
- a fourth flip-flop that receives the second input clock signal as its clock input and a two-count signal from the counter as its D input and provides a fourth clock output;
- a fifth flip-flop that receives the fifth input clock signal as its clock input and the fourth clock output as its D input and provides a fifth clock output;
- a sixth flip-flop that receives the eighth input clock signal as its clock input and the fourth clock output as its D input and provides the sixth clock output;
- a seventh flip-flop that receives the third input clock signal as its clock input and a zero-count signal from the counter as its D input and provides a seventh clock output;
- and
- an eighth flip-flop that receives the sixth input clock signal as its clock input and the seventh clock output as its D input and provides an eighth clock output,
- each clock output after the first having a phase offset of π/4 from the previous clock output.
Dependencies are inferred from the claim text.