Graphics controller integrated circuit without memory interface

A complementary MOS integrated circuit, comprising:

• circuitry for processing, controlling or manipulating video data, the video data for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate having at least two transistors;
• a memory for storing and retrieving at least a portion of said video data, said memory having a capacity of at least 2 megabits;
• and
• a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;
• whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.

A complementary MOS integrated circuit, comprising:

• circuitry for processing data associated with graphics information, the graphics information for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate;
• a memory for storing and retrieving at least a portion of data associated with said graphics information, said memory having a capacity of at least 2 megabits;
• and
• a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;
• whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.

A complementary MOS integrated circuit, comprising:

• circuitry for processing, controlling or manipulating video data, the video data for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate;
• a memory for storing and retrieving at least a portion of said video data, said memory having a capacity of at least 2 megabits;
• and
• a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;
• whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.