Memory unit and method of operating the same
AssigneeSony Corporation
InventorWataru Otsuka
Life of this patent
Estimating the term…
Abstract
A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.
Claims20
A memory unit comprising:
- a plurality of memory cells that respectively have a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target;
- a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells;
- and
- a drive section that selectively changes resistance state of the memory element as the drive target between low resistance state and high resistance state by applying a given electric potential to the word line and the first and the second bit lines,
- wherein in performing setting operation to change resistance state from the high resistance state to the low resistance state for a first memory element located on one word line and in performing resetting operation to change resistance state from the low resistance state to the high resistance state for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.
A method of operating a memory unit, wherein in operating a memory unit including a plurality of memory cells that respectively have a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target and a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells, a given word line electric potential is applied to one word line,
- while an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to a first memory element located on one word line is set to a value higher than that of an electric potential of a bit line on the lower electric potential side corresponding to a second memory element located on the one word line by a given electric potential difference, a given voltage is applied between the first and the second bit lines, and thereby
- setting operation to change resistance state from high resistance state to low resistance state is performed for the first memory element, and resetting operation to change resistance state from the low resistance state to the high resistance state is performed for the second memory element.
A memory unit comprising:
- a plurality of memory cells that respectively have a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target;
- a plurality of resistance elements indicating a fixed resistance value;
- a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells;
- and
- a drive section that selectively changes resistance state of the memory element as the drive target between low resistance state and high resistance state by applying a given electric potential to the word line and the first and the second bit lines,
- wherein in the memory cell, the word line is connected to a gate of the transistor,
- the first bit line is connected to one of a source and a drain in the transistor with the resistance element in between, and
- the second bit line is connected to the other one of the source and the drain in the transistor with the memory element in between.
A method of operating a memory unit, wherein in operating a memory unit that includes a plurality of memory cells respectively having a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target, a plurality of resistance elements indicating a fixed resistance value, and a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells, in which in the memory cell, the word line is connected to a gate of the transistor, the first bit line is connected to one of a source and a drain in the transistor with the resistance element in between, and the second bit line is connected to the other one of the source and the drain in the transistor with the memory element in between,
- a given word line electric potential is applied to one word line,
- while an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to a first memory element located on the one word line is set to a value equal to that of an electric potential of a bit line on the lower electric potential side corresponding to a second memory element located on the one word line,
- a given setting voltage for performing setting operation is applied between the first and the second bit lines corresponding to the first memory element, and a given resetting voltage for performing resetting operation is applied between the first and the second bit lines corresponding to the second memory element, and thereby
- the setting operation to change resistance state from high resistance state to low resistance state is performed for the first memory element, and the resetting operation to change resistance state from the low resistance state to the high resistance state is performed for the second memory element.
Dependencies are inferred from the claim text.