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US 2012/0182048 A1Published application
Radiation hardened circuit design for multinode upsets
AssigneeMicro RDC
InventorPaul Eaton
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AssigneeMicro RDC
InventorPaul Eaton
Estimating the term…
This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques.
A MICE Logic gate containing three (3) split logic gates, each split logic gate containing three (3) logic functions with an isolation device between each connecting node, each logic function containing one (1) NMOS logic block and one (1) PMOS logic block, wherein the NMOS logic block is a single NMOS transistor, and wherein the PMOS logic block is a single PMOS transistor, and wherein the NMOS logic blocks are not in a linear track, and the PMOS logic blocks are not in a linear track.
A MICE logic cell containing three (3) logic functions, with a coupling between each of said logic functions using two (2) or more isolation devices, each logic function containing one (1) NMOS logic block and one (1) PMOS logic block, wherein the NMOS logic block is a single NMOS transistor, and wherein the PMOS logic block is a single PMOS transistor, wherein using two (2) or more isolation devices between the logic functions provides that each NMOS logic block is coupled to two (2) or more of the PMOS logic blocks through at least one of the two (2) or more isolation devices, and provides that each PMOS logic block is coupled to two (2) or more NMOS logic blocks through at least one of the two (2) or more isolation devices, wherein the two or more isolation devices allow the logic cell to contain a struck node, and wherein the two (2) or more of the PMOS logic blocks oppose the two (2) or more NMOS logic blocks and the opposing logic blocks help speed up recovery time of the struck node, and wherein the two or more NMOS logic blocks are not in a linear track, and the two or more PMOS logic blocks are not in a linear track.
A method of isolating a p-mos and n-mos network from a heavy ion strike comprising the step of providing a redundant semiconductor logic chip architecture having at least two identical p-mos logic sub-blocks and at least two identical n-mos logic sub-blocks, wherein the p-mos sub-blocks are isolated from each other and the n-mos sub-blocks are isolated from each other, said isolated sub-blocks isolated using an chip architecture design wherein a heavy ion strike will cause an output which if presented as an input to a downstream circuit of the same architecture will not cause the downstream circuit to change state.
A method of isolating a network having a pull up evaluation function and a pull down evaluation function from a heavy ion strike comprising the step of providing a redundant semiconductor logic chip architecture having at least two identical pull up evaluation functions and at least two identical pull down evaluation functions, wherein the pull up evaluation functions are isolated from each other and the at least two identical pull down evaluation functions are isolated from each other, said isolated pull-up/pull-down evaluation functions isolated using an chip architecture design wherein a heavy ion strike will cause an output which if presented as an input to a downstream circuit of the same architecture will not cause the downstream circuit to change state, and interconnecting these circuits in such a way that double-redundancy prevents single-node upsets (SNUs) and triple-redundancy prevent multi-node upsets (MNUs).
A hardened circuit having a plurality of logic cells for performing a logic function, that comprises:
A split logic function for use as a component of a multiple interlocked (MICE) logic cell where the split logic function comprises:
35-56. (canceled)
Dependencies are inferred from the claim text.