Test mode controller and electronic apparatus with self-testing thereof

Abstract

A test mode controller comprises an enable signal generator, a control signal generator, and a latch. The enable signal generator receives a power signal and a second control signal, and generates a first enable signal and a second enable signal respectively to the latch and the control signal generator. The control signal generator receives a power indicating voltage and a reference voltage, and generates the first control signal to the latch when the first enable signal is enabled. The latch receives the first control signal, and generates the second control signal according to the first control signal when the second enable signal is enabled. The second control signal controls a chip to operate in a test mode or a normal mode. Accordingly, the test mode controller may reduce the test time without a test pin, and may also reduce the chip area and the package cost.

Dependencies are inferred from the claim text.