Symmetric Phase Detector
AssigneeFujitsu Limited
InventorsNikola Nedovic, H. Anders Kristensson, William W. Walker
Life of this patent
Estimating the term…
Abstract
In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell.
Claims13
A circuit comprising:
- a first mixer cell and a second mixer cell, each having respectively a first cell input, a second cell input, and a cell output;
- a first circuit input configured to receive a first input signal having a first phase, the first circuit input being connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell;
- a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value, the second circuit input being connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell;
- and
- a circuit output configured to receive a combined output from respective cell outputs of the first mixer cell and the second mixer cell and output the combined output, the combined output having a current that is proportional to an error offset from the nominal value.
A method comprising:
- receiving at a first circuit input a first input signal having a first phase, the first circuit input being connect to a first cell input of a first mixer cell and a second cell input of a second mixer cell, the first mixer cell and the second mixer cell each having respectively a first cell input, a second cell input and a cell output;
- receiving at a second circuit input a second input signal having a second phase separated from the first phase by a nominal value, the second circuit input being connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell;
- and
- receiving at a circuit output a combined output from respective cell outputs of the first mixer cell and the second mixer cell and output the combined output, the combined output having a current that is proportional to an error offset from the nominal value.
Dependencies are inferred from the claim text.