Semiconductor storage device
AssigneeLapis Semiconductor Co., Ltd.
InventorMasayuki OTSUKA
Life of this patent
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Abstract
A semiconductor storage device has a great number of logic circuits and fuse blocks with its space-saving design. In the semiconductor storage device, a plurality of fuse blocks is arranged in a line or row in the vicinity of a gate array. Each fuse block includes a plurality of fuse pieces arranged in a juxtaposed manner and exposed to the exterior through a fuse window. A power-supply wire and a ground wire extend along the juxtaposed direction of the fuse pieces. Spacing in the vicinity of the gate array is used for arrangement of the fuse blocks.
Claims17
A semiconductor storage device comprising:
- a memory cell array including a plurality of memory cells;
- a plurality of fuse blocks, each said fuse block being connected to a power-supply wire and to a ground wire, each said fuse block including a plurality of fuse pieces arranged in a juxtaposed manner and exposed to an outside through a fuse window, each said fuse block being adapted to store a defective memory address determined by a mode of cutting the fuse pieces, with the power-supply wire and the ground wire extending along a direction in which the fuse pieces are juxtaposed;
- a selection circuit that selects one of the memory cells based on a comparison of a memory address indicated by an access signal to said one of the memory cells with the defective memory address;
- a gate array that processes data corresponding to the memory cell selected by the selection circuit upon receiving a power-supply potential and a ground potential, with the plurality of fuse blocks being arranged in a line in the vicinity of the gate array;
- an additional pattern connected to a same potential as that of one of the power-supply wire and the ground wire which is farther away from the gate array, the additional pattern extending so as to avoid the fuse window;
- and
- a supply wire through which a potential of the additional pattern is supplied to the gate array.
A semiconductor storage device comprising:
- a memory cell array including a plurality of memory cells;
- a plurality of fuse blocks, each said fuse block being connected to a power-supply wire and to a ground wire, each said fuse block including a plurality of fuse pieces arranged in a juxtaposed manner and exposed to an outside through a fuse window, each said fuse block being adapted to store a defective memory address determined by a mode of cutting the fuse pieces;
- a plurality of selection circuits for selecting one of the memory cells based on a comparison of a memory address indicated by an access signal to said one of the memory cells with the defective memory address;
- and
- a gate array for receiving a power-source potential from the power-supply wire and a ground potential from the ground wire and for processing data corresponding to the selected memory cell, with the plurality of selection circuits being arranged in a line in the vicinity of the gate array, the plurality of fuse blocks being arranged in a line between the plurality of selection circuits and the gate array, the power-supply wire and the ground wire extending along a direction in which the fuse pieces are juxtaposed, between the plurality of selection circuits and the gate array.
Dependencies are inferred from the claim text.