Multiple noble metals for lifetime suppression for power semiconductors
AssigneeSolid State Devices, Inc.
InventorAllan Harrison
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Abstract
Certain embodiments combine the use of two or more noble metal impurities (e.g., gold, platinum, palladium, iridium, etc.) to suppress the lifetime of power semiconductors such as diodes. The noble metals may be applied using various methods including, for example, the application of thin films from a liquid suspension of the noble metals (e.g., gold and platinum) and/or alloys thereof onto the wafer and/or the coating the wafer with a layer of the noble metals (e.g., gold and platinum) from high vacuum metal deposition by electron beam or sputtering. The application and drive of the impurities may be simultaneous or sequential.
Claims20
A power semiconductor comprising:
- a silicon substrate;
- gold dopant in the substrate at a concentration of between about 1014 atoms/cm3 and about 1017 atoms/cm3 at a depth of about 1.5 μm;
- and
- platinum dopant in the substrate at a concentration of between about 1014 atoms/cm3 and about 1017 atoms/cm3 at a depth of about 1.5 μm,
- wherein a forward voltage of the power semiconductor is at least as low as a forward voltage of a power semiconductor consisting of only gold dopant in a substrate,
- wherein a reverse breakdown voltage of the power semiconductor is at least as high as a reverse breakdown voltage of a power semiconductor consisting of only gold dopant in a substrate,
- wherein a reverse leakage current of the power semiconductor is lower than a reverse leakage current of a power semiconductor consisting of only gold dopant in a substrate,
- wherein a carrier lifetime is shorter than a carrier lifetime of a power semiconductor consisting of only gold or only platinum dopant in a substrate, and
- wherein a reverse recovery time is shorter than a reverse recovery time of a power semiconductor consisting of only gold or only platinum noble metal dopant in a substrate.
A power semiconductor comprising:
- a substrate;
- a first noble metal dopant in the substrate;
- and
- a second noble metal dopant in the substrate, the second noble metal dopant different than the first noble metal dopant.
A method of manufacturing a power semiconductor, the method comprising:
- applying a first noble metal to a substrate;
- applying a second noble metal to the substrate;
- and
- driving the first noble metal and the second noble metal into the substrate.
Dependencies are inferred from the claim text.