Multi-resistive integrated circuit memory

An integrated circuit memory device, comprising:

• a multi-resistive memory array;
• a circuit connected to the multi-resistive memory array, the circuit to provide a substantially stable voltage to the multi-resistive memory array, the circuit including a capacitor with a layer of conductive material including at least a first portion and a second portion arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per area, and a layer of insulation material disposed at least between the first and second portions;
• and
• a sensor device connected to the multi-resistive memory array to read information from the multi-resistive memory array.