# US 2012/0084778 A1 · Managing execution of mixed workloads in a simultaneous multi-threaded (smt) enabled system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0084778 A1 - Document ID: US20120084778A1 - Status: Published application - Kind: A1 - Application number: 13/304,540 - Filed: 2011-11-25 - Published: 2012-04-05 - Earliest claimed: 2006-06-27 - Assignees: International Business Machines Corporation - Inventors: MICHAEL G. MALL; JAMES B. MOODY; SURESH E. WARRIER - Web page: https://patentgrep.com/patent/US20120084778A1 ## CPC - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 2209/5018: Thread allocation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A kernel of a SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors. ## Claims ### Claim 1 A method for managing a simultaneous multi-threaded (SMT) enabled processor system comprising a plurality of processors each activated to simultaneously execute a plurality of hardware threads, wherein said plurality of processors include an exclusive set of processors to execute work on, said method comprising: scheduling a plurality of tasks of a single-threaded (ST) workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of said ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to run in an idle process, by: setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors; draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors; passing each said hardware thread of said exclusive set of processors to said idle process, wherein said idle process searches each local run queue and cedes each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty; applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors; sending an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and responsive to detecting said remaining hardware threads ceded to said hypervisor, placing each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle process. ### Claim 2 (depends on 1) The method according to claim 1, further comprising: blocking placement of any other tasks on a remaining selection of local run queues of said remaining idle hardware threads per processor within said exclusive set of processors. ### Claim 3 (depends on 1) The method according to claim 1, further comprising: concurrently, executing a SMT workload on the plurality of activated hardware threads of a remaining selection of non-exclusive processors from among the plurality of processors. ### Claim 4 (depends on 1) The method according to claim 1, further comprising: detecting a selection of processors available for inclusion in said exclusive set of processors from among said plurality of processors; and enabling said ST workload to request construction of said exclusive set of processors with processors designated from among said selection of processors. ### Claim 5 (depends on 1) The method according to claim 1, further comprising: receiving said ST workload with a request for said exclusive set of processors solely defined by said number of said plurality of tasks of said ST workload; detecting a selection of processors available for inclusion in said exclusive set of processors from among said plurality of processors; triggering a command to create said exclusive set of processors of a same number as said number of said plurality of tasks with processors designated from among said selection of processors; and attaching said exclusive set of processors to said ST workload. ### Claim 6 (depends on 1) The method according to claim 1, further comprising: receiving, at a kernel layer of said SMT enabled processing system, said ST workload and a selection of processors marked as exclusive for specifying said exclusive set of processors via an application programming interface with an application layer. ### Claim 7 A simultaneous multi-thread (SMT) enabled processing system, comprising a plurality of processors each enabled for simultaneous execution of multiple hardware threads, wherein said plurality of processors include an exclusive set of processors to execute work on, comprising; a kernel, stored on a memory and operative to schedule a single-threaded (ST) workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of the ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to run in an idle process, further comprising: the kernel, operative to set a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors; the kernel, operative to drain any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors; the kernel, operative to pass each said hardware thread of said exclusive set of processors to said idle process, wherein said idle process searches each local run queue and cedes each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty; the kernel, operative to apply each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors; the kernel, operative to send an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and the kernel, responsive to detecting said remaining hardware threads ceded to said hypervisor, operative to place each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle process. ### Claim 8 (depends on 7) The system according to claim 7, further comprising: the kernel, operative to block placement of any other tasks on a remaining selection of local run queues of said remaining idle hardware threads per processor within said exclusive set of processors. ### Claim 9 (depends on 7) The system according to claim 7, further comprising: the kernel, operative to concurrently execute a SMT workload on the plurality of activated hardware threads of a remaining selection of non-exclusive processors from among the plurality of processors. ### Claim 10 (depends on 7) The system according to claim 7, further comprising: the kernel, operative to detect a selection of processors available for inclusion in said exclusive set of processors from among said plurality of processors; and the kernel, operative to enable said ST workload to request construction of said exclusive set of processors with processors designated from among said selection of processors. ### Claim 11 (depends on 7) The system according to claim 7, further comprising: the kernel, operative to receive said ST workload with a request for said exclusive set of processors solely defined by said number of said plurality of tasks of said ST workload; the kernel, operative to detect a selection of processors available for inclusion in said exclusive set of processors from among said plurality of processors; the kernel, operative to trigger a command to create said exclusive set of processors of a same number as said number of said plurality of tasks with processors designated from among said selection of processors; and the kernel, operative to attach said exclusive set of processors to said ST workload. ### Claim 12 (depends on 7) The system according to claim 7, further comprising: the kernel, operative to receive, at a kernel layer of said SMT enabled processing system, said ST workload and a selection of processors marked as exclusive for specifying said exclusive set of processors via an application programming interface with an application layer. ### Claim 13 A computer program product for managing a simultaneous multi-threaded (SMT) enabled processor system comprising a plurality of processors each activated to simultaneously execute a plurality of hardware threads, wherein said plurality of processors include an exclusive set of processors to execute work on, said computer program product tangibly embodied in a computer-readable storage medium and comprising computer executable instructions which cause a computer to: schedule a plurality of tasks of a single-threaded (ST) workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of said ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to run in an idle process, further comprising computer executable instructions which cause a computer to: set a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors; drain any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors; pass each said hardware thread of said exclusive set of processors to said idle process, wherein said idle process searches each local run queue and cedes each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty; apply each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors; send an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and responsive to detecting said remaining hardware threads ceded to said hypervisor, place each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle process. ### Claim 14 (depends on 13) The computer program product according to claim 13, further comprising computer executable instructions which cause a computer to: block placement of any other tasks on a remaining selection of local run queues of said remaining idle hardware threads per processor within said exclusive set of processors. ### Claim 15 (depends on 13) The computer program product according to claim 13, further comprising computer executable instructions which cause a computer to: concurrently, execute a SMT workload on the plurality of activated hardware threads of a remaining selection of non-exclusive processors from among the plurality of processors. ### Claim 16 (depends on 13) The computer program product according to claim 13, further comprising computer executable instructions which cause a computer to: detect a selection of processors available for inclusion in said exclusive set of processors from among said plurality of processors; and enabling said ST workload to request construction of said exclusive set of processors with processors designated from among said selection of processors. ### Claim 17 (depends on 13) The computer program product according to claim 13, further comprising computer executable instructions which cause a computer to: receive said ST workload with a request for said exclusive set of processors solely defined by said number of said plurality of tasks of said ST workload; detect a selection of processors available for inclusion in said exclusive set of processors from among said plurality of processors; trigger a command to create said exclusive set of processors of a same number as said number of said plurality of tasks with processors designated from among said selection of processors; and attach said exclusive set of processors to said ST workload. ### Claim 18 (depends on 13) The computer program product according to claim 13, further comprising computer executable instructions which cause a computer to: receive, at a kernel layer of said SMT enabled processing system, said ST workload and a selection of processors marked as exclusive for specifying said exclusive set of processors via an application programming interface with an application layer.