# US 2012/0084589 A1 · Hardware Dynamic Cache Power Management

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- Number: US 2012/0084589 A1
- Document ID: US20120084589A1
- Status: Published application
- Kind: A1
- Application number: 12/894,516
- Filed: 2010-09-30
- Published: 2012-04-05
- Earliest claimed: 2010-09-30
- Assignees: Apple Inc.
- Inventors: Timothy J. Millet; Erik P. Machnicki; Deniz Balkan; Vijay Gupta
- Web page: https://patentgrep.com/patent/US20120084589A1

## CPC

- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

## Claims

### Claim 1

An apparatus comprising:
a memory configured to store data identifying a first set of operations to be performed prior to powering down a circuit block and a second set of operations to be performed subsequent to powering up the circuit block;
a control circuit coupled to receive a request to power the circuit block down during a time that processors in a system that includes the memory and control circuit are powered down, wherein the control circuit is configured to perform the corresponding first set of operations identified in the memory responsive to the request.

### Claim 2 (depends on 1)

The apparatus as recited in claim 1 wherein the first set of operations comprise a first plurality of register write operations for a first plurality of registers in the circuit block, and wherein the data in the memory comprises a first plurality of addresses identifying the plurality of registers and a first plurality of data values to be written to the first plurality of registers, and wherein the second set of operations comprise a second plurality of register write operations for a second plurality of registers in the circuit block, and wherein the data in the memory comprises a second plurality of addresses identifying the second plurality of registers and a second plurality of data values to be written to the second plurality of registers.

### Claim 3 (depends on 2)

The apparatus as recited in claim 2 wherein a first register is included in both the first plurality of registers and the second plurality of registers.

### Claim 4 (depends on 1)

The apparatus as recited in claim 1 wherein the memory comprises one or more registers programmable by software with the first set of operations and the second set of operations.

### Claim 5 (depends on 1)

The apparatus as recited in claim 1 wherein the control circuit is further configured to receive a request to power a circuit block up during a time that the processors in the system are powered down, and wherein the control circuit is configured to perform the corresponding second set of operations identified in the memory responsive to the request to power the circuit block up.

### Claim 6

A system comprising:
one or more processors;
a cache coupled to the one or more processors; and
a bridge coupled to the cache and configured to couple to one or more peripherals, wherein the bridge comprises a plurality of registers that are programmable with data representing a first plurality of operations to be performed prior to powering down the cache and a second plurality of operations to be performed during a power up of the cache, and wherein the bridge is configured to perform the first plurality of operations in response to a power down event for the cache and to perform the second plurality of operations in response to a power up event for the cache.

### Claim 7 (depends on 6)

The system as recited in claim 6 wherein the cache comprises a plurality of configuration registers, and wherein at least some of the second plurality of operations are writes to one or more of the plurality of configuration registers, and wherein the plurality of registers are programmed with addresses of the one or more of the plurality of configuration registers and the values to be written to the one or more of the plurality of configuration registers.

### Claim 8 (depends on 6)

The system as recited in claim 6 further comprising a power manager configured to generate the power down event responsive to detecting that the one or more processors are powered down and further responsive to detecting that there are no pending operations from the one or more peripherals.

### Claim 9 (depends on 8)

The system as recited in claim 8 wherein the bridge is configured to acknowledge the power down event responsive to completing the first plurality of operations.

### Claim 10 (depends on 9)

The system as recited in claim 9 wherein the power manager is configured to generate the power up event, and wherein the bridge is configured to acknowledge the power up event responsive to completing the second plurality of operations.

### Claim 11 (depends on 6)

The system as recited in claim 6 wherein the plurality of registers include an indication for each operation represented in the plurality of registers, the indication indicating whether the operation is one of the first plurality of operations or the second plurality of operations.

### Claim 12

A method comprising:
detecting that a cache is to be powered up in a system including one or more processors coupled to the cache, wherein the one or more processors are powered down at a time of the detecting;
issuing a request to a bridge that is coupled to the cache and one or more peripherals; and
the bridge responding to the request by performing a plurality of operations stored in the bridge to initialize one or more configuration registers in the cache.

### Claim 13 (depends on 12)

The method as recited in claim 12 wherein each operation is represented by an address of the configuration register and a value to be written into the configuration register.

### Claim 14 (depends on 12)

The method as recited in claim 12 further comprising:
detecting that the cache is to be powered down;
issuing a second request to the bridge; and
the bridge responding to the second request by performing one or more second operations stored in the bridge.

### Claim 15 (depends on 14)

The method as recited in claim 14 wherein the one or more second operations cause a synchronization operation in the cache.

### Claim 16 (depends on 14)

The method as recited in claim 14 further comprising:
the bridge determining that the one or more second operations are complete;
the bridge acknowledging the second request responsive to the determining; and
powering down the cache responsive to the bridge acknowledging.

### Claim 17

A computer accessible storage medium storing a plurality of instructions which, when executed in a system:
initialize one or more configuration registers of a cache; and
write corresponding data for the configuration registers in a memory in a bridge to automatically restore the configuration registers subsequent to a power down event and a subsequent power up event.

### Claim 18 (depends on 17)

The computer accessible storage medium as recited in claim 17 wherein the plurality of instructions, when executed:
write a flag corresponding to each corresponding data for each configuration register indicating that the corresponding data is to be written during the power up event.

### Claim 19 (depends on 18)

The computer accessible storage medium as recited in claim 18 wherein the plurality of instructions, when executed:
write data to the memory in the bridge corresponding to one or more additional register write operations to be performed during a power down event; and
write the flag corresponding to the additional register write operations to indicate that the one or more additional register write operations are to be performed during the power down event.

### Claim 20 (depends on 19)

The computer accessible storage medium as recited in claim 19 wherein the one or more additional register write operations cause a synchronization operation in the cache.

### Claim 21

A system comprising:
one or more processors;
a cache coupled to the one or more processors, the cache comprising a plurality of configuration registers that are programmable to control operation of the cache;
a power manager coupled to the processors and the cache, wherein the power manager is configured to control power up and power down of the processors and the cache; and
a bridge coupled to the cache and the power manager, wherein the bridge is configured to couple to one or more peripherals, and wherein the bridge comprises a plurality of registers programmable with address and data pairs representing register writes to the plurality of configuration registers, and wherein the bridge is configured to perform at least a first register write to a first configuration register of the plurality of configuration registers in response to a power down event for the cache signalled by the power manager, and wherein the bridge is configured to perform at least a second register write to a second configuration register of the plurality of configuration register in response to a power up event for the cache.

### Claim 22 (depends on 21)

The system as recited in claim 21 wherein the bridge is configured to determine that the first configuration register write is complete, and wherein the bridge is configured to signal the power manager in response to determining that the first configuration register write is complete, and wherein the power manager is configured to power down the cache responsive to the signal from the bridge.