# US 2012/0084577 A1 · Charge pump apparatus, a memory integrated circuit and methods of power supply > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0084577 A1 - Document ID: US20120084577A1 - Status: Published application - Kind: A1 - Application number: 13/315,385 - Filed: 2011-12-09 - Published: 2012-04-05 - Earliest claimed: 2002-03-06 - Assignees: Micron Technology, Inc. - Inventors: Dumitru Cioaca - Web page: https://patentgrep.com/patent/US20120084577A1 ## CPC - G11C 16/30: Power supply circuits - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described. ## Claims ### Claim at position 1 1-13. (canceled) ### Claim 14 A method of supplying current to a device having a plurality of data inputs comprising: sensing a number of zero bits on said plurality of data inputs; activating a number of charge pump circuits proportional to said number of zero bits; supplying a level of current to said device proportional to said number of charge pump circuits, wherein said level of current is adapted to meet a requirement of said device related to said number of zero bits. ### Claim at position 3 15-17. (canceled) ### Claim 18 A method of supplying power to a plurality of memory cells of a memory integrated circuit comprising: sensing a number of zero bits to be written to a corresponding number of said plurality of memory cells; and activating one or more power supplies in relation to said sensed number of zero bits. ### Claim 19 A method of controlling a charge pump comprising: predicting a required level of current; activating a portion of a multi-portion charge pump so as to supply said required level of current to an output of the charge pump. ### Claim 20 (depends on 19) The method of claim 19, wherein said predicting a required level of current further comprises: sensing an input to a flash memory device; determining a required level of programming current based on said input and a known characteristic of said device. ### Claim 21 (depends on 20) The method of claim 20, wherein said input further comprises: a digital data signal at a data input of said device. ### Claim 22 (depends on 20) The method of claim 20, wherein said known characteristic of said device further comprises a known programming current per memory cell. ### Claim 23 (depends on 19) The method of claim 19, wherein said predicting a required level of current further comprises: sensing a plurality of input signals on a data bus operatively connected to a device, said data bus having a respective plurality of data bit lines; determining a number of said plurality of input signals corresponding to a first data state; predicting said required level of current equal to said number multiplied by a predefined quantity of current. ### Claim at position 10 24-26. (canceled) ### Claim 27 An open loop charge pump control method comprising: sensing a data input, said data input adapted to control an electrical load; switchingly connecting one or more of a plurality of charge pumps in response to said data input, as sensed, wherein said plurality of charge pumps are each adapted to be switchingly connected to said electrical load to supply said electrical load with electrical power; and operating said electrical load so as to draw a level of current within a particular range of currents from said one or more of said switchingly connected plurality of charge pumps. ### Claim 28 (depends on 27) The open loop charge pump control method of claim 27, wherein said sensing a data input further comprises sensing a plurality of data states on a respective plurality of data input lines. ### Claim 29 (depends on 27) The open loop charge pump control method of claim 27, wherein said sensing a data input further comprises sensing a plurality of data states of a serial data transmission. ### Claim 30 (depends on 27) The open loop charge pump control method of claim 27, wherein said electrical load comprises a portion of a memory integrated circuit. ### Claim 31 (depends on 30) The open loop charge pump control method of claim 30, wherein said memory integrated circuit comprises a flash memory integrated circuit. ### Claim 32 An open loop charge pump control method comprising: sensing a data input, said data input being operatively connected to an electrical load; turning on one of a plurality of charge pumps in response to said data input, wherein said plurality of charge pumps are each operatively connected to said electrical load to supply said electrical load with electrical power; and operating said electrical load so as to draw a level of current affected by said turning on of said one charge pump. ### Claim 33 A charge pump apparatus comprising: means for sensing a number of bits of a data input having a particular state; a plurality of charge pump circuits; and means for activating one or more of said plurality of charge pumps circuits based on said number of bits of data having said particular state, wherein said charge pump apparatus is adapted to provide a particular amount of power to a load circuit. ### Claim 34 (depends on 33) The charge pump apparatus of claim 33, wherein said means for sensing a number of bits comprises digital sensing means. ### Claim 35 (depends on 33) The charge pump apparatus of claim 33, wherein said means for sensing a number of bits comprises analog sensing means. ### Claim at position 20 36-37. (canceled) ### Claim 38 A memory integrated circuit comprising: a plurality of memory cells each adapted to be programmed into a respective plurality of logic states; a plurality of data lines adapted to convey a plurality of data signals to said plurality of memory cells respectively, said data signals corresponding to said logic states respectively; a control system adapted to sense said plurality of data signals; a plurality of charge pump circuits operatively connected to said control system and adapted to be controlled by said control system; and a plurality of conductors adapted to conduct power from said charge pump circuits to said memory cells. ### Claim at position 22 39-43. (canceled)