# US 2012/0084528 A1 · System with Internal Memory for Storing Data or a Portion of Data Written to External Memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0084528 A1 - Document ID: US20120084528A1 - Status: Published application - Kind: A1 - Application number: 13/315,763 - Filed: 2011-12-09 - Published: 2012-04-05 - Earliest claimed: 2008-03-19 - Assignees: Lantiq Beteiligungs-GmbH & Co. KG - Inventors: Chunfeng Hu - Web page: https://patentgrep.com/patent/US20120084528A1 ## CPC - G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems - G06F 2212/251: Local memory within processor subsystem - G06F 2212/253: Centralized memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system includes an internal memory configured to store data, a memory access controller, logic, and a processor. The memory access controller is operable to read data from a peripheral device in response to an event external to the system, write the data to memory external to the system and forward the data or a portion of the data to the internal memory. The logic is operable to track which portion of the data is stored in both the external memory and the internal memory. The processor has one or more caches logically and physically separated from the internal memory. The processor is operable to retrieve the data forwarded to the internal memory and use the retrieved data to begin servicing the event. ## Claims ### Claim 1 A method of processing data in an embedded system, comprising: writing data read from a peripheral device in response to an event external to the embedded system; writing the data or a portion of the data to memory internal to the embedded system; recording which portion of the data is stored in both the external memory and the internal memory; retrieving the data written to the internal memory of the embedded system by a processor included in the embedded system, the processor having one or more caches logically and physically separated from the internal memory; and using the data retrieved by the processor to begin servicing the event. ### Claim 2 (depends on 1) The method of claim 1, wherein the data is written to the external memory and the data or a portion of the data is written to the internal memory of the embedded system in parallel. ### Claim 3 (depends on 1) The method of claim 1, wherein writing the data or a portion of the data to the internal memory of the embedded system comprises writing packet header information included with the data to the internal memory of the embedded system. ### Claim 4 (depends on 1) The method of claim 1, wherein recording which portion of the data is stored in both the external memory and the internal memory comprises: updating a multi-entry external memory ingress queue allocated to the peripheral device responsive to the data being written to the external memory and the data or a portion of the data being written to the internal memory of the embedded system; and updating a multi-entry internal memory ingress queue responsive to the data or a portion of the data being written to the internal memory of the embedded system. ### Claim 5 (depends on 4) The method of claim 4, wherein updating the multi-entry external memory ingress queue comprises: identifying the first entry of the multi-entry external memory ingress queue that contains invalid data; identifying the first entry of the multi-entry external memory ingress queue that contains valid data yet to be written to the internal memory of the embedded system; and updating the entry of the multi-entry external memory ingress queue in which at least a portion of the data read from the peripheral device is stored. ### Claim 6 (depends on 5) The method of claim 5, wherein updating the entry of the multi-entry external memory ingress queue in which at least a portion of the data read from the peripheral device is stored comprises at least one of: indicating whether the entry contains valid data and the size of the valid data; indicating an address of the external memory where a beginning portion of the data is stored; indicating whether the entry contains data written to the internal memory of the embedded system; and indicating whether the entry contains invalid data after the processor completes servicing of the event. ### Claim 7 (depends on 4) The method of claim 4, wherein updating the multi-entry internal memory ingress queue comprises: identifying the first entry of the internal memory ingress queue that contains invalid data; identifying the first entry of the internal memory ingress queue that contains valid data yet to be read by the processor; and updating the entry of the internal memory ingress queue in which at least a portion of the data is stored. ### Claim 8 (depends on 7) The method of claim 7, wherein updating the entry of the internal memory ingress queue in which at least a portion of the data is stored comprises at least one of: indicating whether the entry contains valid data; indicating which entry of the multi-entry external memory ingress queue contains data corresponding to the data or a portion of the data written to the internal memory of the embedded system; and indicating whether the entry contains invalid data after the processor completes servicing of the event. ### Claim 9 A system, comprising: an internal memory configured to store data; a memory access controller operable to read data from a peripheral device in response to an event external to the system, write the data to memory external to the system and forward the data or a portion of the data to the internal memory; logic operable to track which portion of the data is stored in both the external memory and the internal memory; and a processor having one or more caches logically and physically separated from the internal memory, the processor operable to retrieve the data forwarded to the internal memory and use the retrieved data to begin servicing the event. ### Claim 10 (depends on 9) The system of claim 9, wherein the logic is operable to: update a multi-entry external memory ingress queue allocated to the peripheral device responsive to the data being written to the external memory and the data or a portion of the data being forwarded to the internal memory; and update a multi-entry internal memory ingress queue responsive to the data or a portion of the data being forwarded to the internal memory. ### Claim 11 (depends on 10) The system of claim 10, wherein the logic is operable to: identify the first entry of the multi-entry external memory ingress queue that contains invalid data; identify the first entry of the multi-entry external memory ingress queue that contains valid data yet to be forwarded to the internal memory; and update the entry of the multi-entry external memory ingress queue in which at least a portion of the data read from the peripheral device is stored. ### Claim 12 (depends on 11) The system of claim 11, wherein the logic is operable to at least one of: indicate whether the entry contains valid data and the size of the valid data; indicate an address of the external memory where a beginning portion of the data is stored; indicate whether the entry contains data forwarded to the internal memory; and indicate whether the entry contains invalid data after the processor completes servicing of the event. ### Claim 13 (depends on 11) The system of claim 11, wherein the logic is operable to: identify the first entry of the internal memory ingress queue that contains invalid data; identify the first entry of the internal memory ingress queue that contains valid data yet to be read by the processor; and update the entry of the internal memory ingress queue in which at least a portion of the forwarded data is stored. ### Claim 14 (depends on 13) The system of claim 13, wherein the logic is operable to at least one of: indicate whether the entry contains valid data; indicate which entry of the multi-entry external memory ingress queue contains data corresponding to the data forwarded to the internal memory; and indicate whether the entry contains invalid data after the processor completes servicing of the event. ### Claim 15 (depends on 9) The system of claim 9, wherein the memory access controller is operable to forward a quantity of the data to the internal memory corresponding to a configuration parameter provided to the system. ### Claim 16 (depends on 9) The system of claim 9, wherein the processor is operable to continue servicing the event based on a remainder of the data retrieved from the external memory. ### Claim 17 (depends on 9) The system of claim 9, wherein the memory access controller, logic and processor are integrated on the same chip. ### Claim 18 (depends on 9) The system of claim 9, wherein the data includes one or more commands to be executed by the processor. ### Claim 19 (depends on 9) The system of claim 9, wherein the processor is operable to load the data retrieved from the internal memory into at least one cache of the processor. ### Claim 20 (depends on 19) The system of claim 19, wherein the processor is operable to load the data retrieved from the internal memory into at least one cache of the processor directly from the internal memory.