# US 2012/0084513 A1 · Circuit and method for determining memory access, cache controller, and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0084513 A1 - Document ID: US20120084513A1 - Status: Published application - Kind: A1 - Application number: 13/232,418 - Filed: 2011-09-14 - Published: 2012-04-05 - Earliest claimed: 2010-10-01 - Assignees: Fujitsu Semiconductor Limited - Inventors: Kazuhiko OKADA - Web page: https://patentgrep.com/patent/US20120084513A1 ## CPC - G06F 12/0862: with prefetch - G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination. ## Claims ### Claim 1 A memory access determination circuit comprising: a counter that switches between a first reference value and a second reference value in accordance with a control signal and generates a count value based on the first reference value or the second reference value; a controller that performs a cache determination based on an address corresponding to the count value and generates the control signal in accordance with the cache determination; and a changing unit that changes the second reference value in accordance with the cache determination. ### Claim 2 (depends on 1) The memory access determination circuit according to claim 1, wherein the changing unit includes a hit rate calculation unit, which calculates a cache hit rate based on the cache determination, and changes the second reference value based on the cache hit rate. ### Claim 3 (depends on 2) The memory access determination circuit according to claim 2, wherein the hit rate calculation unit calculates a cache miss rate based on the cache determination indicating that a cache miss has occurred at an address corresponding to the count value generated in accordance with the second reference value. ### Claim 4 (depends on 1) The memory access determination circuit according to claim 1, wherein: the second reference value includes a reference value for generating a first address in a first cycle when the cache determination indicates the cache miss and a reference value for generating a second address in a cycle following the first cycle; the changing unit calculates a cache miss rate based on the cache determination indicating that a cache miss has occurred at an address corresponding to the count value generated in accordance with the second reference value and changes the reference value for generating the first address based on the cache miss rate; and the changing unit calculates a cache hit rate based on the cache determination and changes the reference value for generating the second address based on the cache hit rate. ### Claim 5 (depends on 1) The memory access determination circuit according to claim 1, wherein the changing unit calculates a cache hit rate based on the cache determination and changes the second reference value, based on the calculated cache hit rate and a previously calculated and held cache hit rate, to increase a subsequent cache hit rate. ### Claim 6 (depends on 1) The memory access determination circuit according to claim 1, wherein when the cache determination indicates a cache miss, the controller performs prefetching on a main memory by using the address corresponding to the count value as a prefetch address, and the controller stores data read from the main memory in a cache memory. ### Claim 7 (depends on 1) The memory access determination circuit according to claim 1, wherein the counter holds the count value generated in accordance with the first reference value when the cache determination indicates a cache miss, and switches the count value generated in accordance with the second reference value to the count value generated and held in accordance with the first reference value in correspondence with an accessing situation of the main memory based on an address determined as the cache miss. ### Claim 8 A cache controller comprising: a cache determination unit that performs a cache determination, based on an address corresponding to a count value output from a counter in accordance with a reference value, and outputs a control signal; and a changing unit that changes the reference value with the control signal so that a cache hit rate increases when the cache determination indicates a cache miss. ### Claim 9 (depends on 8) The cache controller according to claim 8, wherein: the reference value includes a first value and a second value that are selectively used when the cache determination indicates the cache miss; and the changing unit changes the first value based on a cache miss rate calculated upon occurrence of the cache miss and changes the second value based on a cache hit rate calculated upon the occurrence of the cache miss. ### Claim 10 A method for determining memory access, the method comprising: switching between a first reference value and a second reference value in accordance with a control signal; generating a count value based on the first reference value or the second reference value; performing a cache determination based on an address corresponding to the count value; generating the control signal in accordance with the cache determination; and changing the second reference value in accordance with the cache determination. ### Claim 11 (depends on 10) The method according to claim 10, wherein: the second reference value includes a first value and a second value that are selectively used when the cache determination indicates the cache miss; and the changing the second reference value includes: changing the first value based on a cache miss rate calculated upon occurrence of the cache miss; and changing the second value based on a cache hit rate calculated upon the occurrence of the cache miss. ### Claim 12 An electronic device comprising: a main memory; a cache memory that operates at a higher speed than the main memory; a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value; a controller that performs a cache determination based on an address corresponding to the count value and generates the control signal in accordance with the cache determination; and a changing unit that changes the second reference value in accordance with the cache determination.