# US 2012/0084478 A1 · Stacked die with vertically-aligned conductors and methods for making the same

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- Number: US 2012/0084478 A1
- Document ID: US20120084478A1
- Status: Published application
- Kind: A1
- Application number: 12/895,098
- Filed: 2010-09-30
- Published: 2012-04-05
- Earliest claimed: 2010-09-30
- Assignees: Apple Inc.
- Inventors: Nir J. Wakrat; Nick Seroff; Anthony Fai
- Web page: https://patentgrep.com/patent/US20120084478A1

## CPC

- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device.

## Claims

### Claim 1

A non-volatile memory package, comprising:
a plurality of dies each having a rectangular shape including a length, a width, a top surface, a bottom surface, and edges, the rectangular shape is divided into four quadrants, and each die is constructed to have bus interface connectors extending from a predetermined one of the quadrants such that each interface connector extends beyond at least one edge of the predetermined quadrant,
wherein the plurality of dies are arranged in a vertical stack, the vertical stack having multiple non-overlapping zones, and each die is oriented such that the predetermined quadrant for each die is positioned in a different one of the non-overlapping zone;
controller circuitry mounted on the top surface of a top die in the vertical stack; and
a plurality of conductors that interface the controller circuitry to the bus interface connectors.

### Claim 2 (depends on 1)

The non-volatile memory package of claim 1, wherein each conductor includes a vertical portion that is external to the edges of the die and interfaces with one of the bus interface connectors and a horizontal portion that interfaces with the control circuitry.

### Claim 3 (depends on 1)

The non-volatile memory package of claim 1, wherein each conductor is electrically insulated.

### Claim 4 (depends on 1)

The non-volatile memory package of claim 1, wherein the plurality of dies are nand flash die.

### Claim 5 (depends on 1)

The non-volatile memory package of claim 1, wherein each of the plurality of dies are substantially the same.

### Claim 6 (depends on 1)

The non-volatile memory package of claim 1, wherein the control circuitry comprises error correction circuitry.

### Claim 7

A silicon package, comprising:
a plurality of die arranged in a vertical stack, each die having bus interface connectors protruding away from the die;
controller circuitry mounted to a surface of one of the die; and
conductors that electrically couple the controller circuitry to the interface bus connectors, wherein the conductors are mounted external to the plurality of die.

### Claim 8 (depends on 7)

The silicon package of claim 7, wherein each die in the plurality of die is constructed to have its interface bus connectors located in the same location, and wherein each die is arranged in the vertical stack so that the conductors do not overlap each other.

### Claim 9 (depends on 7)

The silicon package of claim 7, wherein each die in the plurality of die is constructed to have its interface bus connector located in a location different than the location of each other die.

### Claim 10 (depends on 7)

The silicon package of claim 7, wherein the conductors do not overlap each other and are electrically isolated from each other.

### Claim 11 (depends on 7)

The silicon package of claim 7, wherein a portion of at least one conductor is aligned perpendicular to a plane of a top surface of the vertical stack.

### Claim 12 (depends on 7)

The silicon package of claim 7, further comprising:
an insulation material disposed between each die in the stack.

### Claim 13

A method for making a stacked non-volatile die package, the method comprising:
providing a plurality of NVM dies, each die having a substantially similar construction that includes interface bus connectors that extend away from at least one edge of the die;
orienting the plurality of dies such that the interface bus connectors for any one die are positioned in a zone that does not overlap with the interface bus connectors of the other dies;
stacking the oriented plurality of dies;
mounting control circuitry to a surface of one of the die; and
electrically coupling the control circuitry to the interface bus connectors with a plurality of conductors.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
placing a dielectric material between each of the plurality of dies to electrically isolate each die from each other.

### Claim 15

A method for making a stacked die package, the method comprising:
providing a plurality of dies, each die constructed to have similar physical dimensions and include interface bus connectors that extend away from a predetermined portion of the die, wherein the predetermined portion is different for each die;
stacking the plurality of dies;
mounting control circuitry to a surface of one of the die; and
electrically coupling the control circuitry to the interface bus connectors with a plurality of conductors.