# US 2012/0084241 A1 · Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

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- Number: US 2012/0084241 A1
- Document ID: US20120084241A1
- Status: Published application
- Kind: A1
- Application number: 12/895,791
- Filed: 2010-09-30
- Published: 2012-04-05
- Earliest claimed: 2010-09-30
- Assignees: International Business Machines Corporation
- Inventors: Daniel J. Friedman; Seongwon Kim; Chung H. Lam; Dharmendra S. Modha; Bipin Rajendran; Jose A. Tierno
- Web page: https://patentgrep.com/patent/US20120084241A1

## CPC

- G06N 3/06: Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N 3/088: Non-supervised learning, e.g. competitive learning
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N 3/0495: Quantised networks; Sparse networks; Compressed networks
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

## Claims

### Claim 1

A neuromorphic network for producing spike-timing dependent plasticity, comprising:
a plurality of electronic neurons;
an interconnect circuit interconnecting the plurality of electronic neurons, the interconnect circuit comprising:
a plurality of plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths;
wherein each synaptic device comprises a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor;
wherein the source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

### Claim 2 (depends on 1)

The neuromorphic network of claim 1, wherein:
each variable state resistor comprises a phase change memory device;
each transistor device comprises a field effect transistor; and
wherein the source terminal of the transistor functions as an axon, the gate terminal of the transistor functions as a membrane and the second terminal of the variable state resistor functions as a dendrite.

### Claim 3 (depends on 2)

The neuromorphic network of claim 2, further comprising:
a timing controller configured to generate a timing signal for controlling phased operation of the electronic neurons, the timing signal providing a sequence of phases, wherein activity of each electronic neuron is confined to said phases such that the synaptic devices provide spike-timing dependent plasticity based on the activity of the electronic neurons in a time phased fashion.

### Claim 4 (depends on 3)

The neuromorphic network of claim 3, wherein:
said sequence of phases comprises: an evaluation phase, a communication phase, a first programming phase and a second programming phase; and
activity of each electronic neuron at any instant in time is controlled by the timing signal, the neuron activity comprising: evaluation activity, communication activity and programming activity.

### Claim 5 (depends on 4)

The neuromorphic network of claim 4, further comprising:
a time counter that keeps track of the time elapsed since a total integrated input for the neuron exceeds a pre-determined threshold value;
wherein in the evaluation phase, evaluation activity of a neuron comprises determining if a total integrated input for the neuron exceeds a pre-determined threshold value to generate a spike, and if the integrated input exceeds the pre-determined threshold value in the evaluation phase, then the time counter is reinitialized.

### Claim 6 (depends on 5)

The neuromorphic network of claim 5, wherein:
in the communication phase, communication activity of a neuron comprises: if the integrated input exceeded the pre-determined threshold value in the evaluate phase, then generating a read signal on an axon path for the neuron, generating a bias potential on a membrane path for the neuron, and integrating signals received on a dendrite path for the neuron.

### Claim 7 (depends on 6)

The neuromorphic network of claim 6, wherein:
in the programming phase, programming activity of a neuron comprises generating a signal for decreasing or increasing the resistance of a variable state resistor in a synaptic device connected between the neuron and another neuron.

### Claim 8 (depends on 7)

The neuromorphic network of claim 7, wherein:
in the programming phase:
during a first programming interval, programming activity of a neuron comprises the neuron generating set pulse on a dendrite path for the neuron if the integrated input exceeds the pre-determined threshold value in the evaluation phase; and
during a second programming interval, programming activity of the neuron comprises the neuron generating a reset pulse on a membrane path for the neuron if the integrated input exceeded the pre-determined threshold value in the evaluate phase.

### Claim 9 (depends on 8)

The neuromorphic network of claim 8, wherein:
in the programming phase:
during the first programming interval, programming activity of a neuron further comprises the neuron generating an enable pulse of decreasing strength, in amplitude or probability of occurrence, on a membrane path for the neuron, as a function of the value of a time counter that keeps track of the time elapsed since said total integrated input exceeds a pre-determined threshold value.

### Claim 10 (depends on 8)

The neuromorphic network of claim 8, wherein:
in the programming phase:
during the second programming interval, programming activity of a neuron further comprises the neuron generating an enable pulse of decreasing strength, in amplitude or probability of occurrence, on a dendrite path for the neuron, as a function of the value of a time counter that keeps track of the time elapsed since said total integrated input exceeds a pre-determined threshold value.

### Claim 11 (depends on 10)

The neuromorphic network of claim 10, wherein:
the interconnect circuit comprises a cross-bar array coupled to the plurality of electronic neurons to interconnect the plurality of electronic neurons, the cross-bar array comprises:
plurality of axon paths, dendrite paths and membrane paths, such that the dendrites paths are orthogonal to the axon path and membrane paths;
such that each synaptic device is at a cross-point junction of the cross-bar array coupled between a dendrite path and an axon path, and between the dendrite path and membrane path;
wherein the time phased activity of the electronic neurons is changing the state of the variable state resistors as a function of time since a last spiking of an electronic neuron firing a spiking signal.

### Claim 12

A probabilistic asynchronous neuromorphic network for producing spike-timing dependent plasticity, comprising:
a plurality of electronic neurons;
an interconnect circuit coupled to the plurality of electronic neurons, the interconnect circuit comprising:
a plurality of axons and a plurality of dendrites wherein the axons and dendrites are orthogonal to one another;
plural synaptic devices configured for interconnecting the electronic neurons via axons and dendrites, each synaptic device comprising a binary state memory device at a cross-point junction of the interconnect circuit coupled between a dendrite and an axon;
a plurality of dendrite drivers corresponding to the plurality of dendrites and a plurality of axon drivers corresponding to the plurality of axons, wherein each dendrite driver is coupled to a dendrite at a first side of the interconnect circuit and each axon driver is coupled to an axon at a second side of the interconnect circuit;
wherein an axon driver and a dendrite driver coupled by a binary state memory generate stochastic signals capable of changing the state of the binary state memory device as a function of time.

### Claim 13 (depends on 12)

The network of claim 12, wherein:
the stochastic signals are capable of changing the state of the binary state memory device as a function of time since a last spiking of an electronic neuron firing a spiking signal into the axon driver and the dendrite driver, such that the binary state memory device provides spike-timing dependent plasticity.

### Claim 14 (depends on 13)

The network of claim 13, further comprising:
a timing controller configured to generate a timing signal for controlling phased operation of the electronic neurons, the timing signal providing a sequence of phases, wherein activity of each electronic neuron is confined to said phases such that the synaptic devices provide spike-timing dependent plasticity based on the activity of the electronic neurons in a time phased fashion, wherein:
said sequence of phases comprises: an evaluation phase, a communication phase, a first programming phase and a second programming phase; and
activity of each electronic neuron at any instant in time is controlled by the timing signal, the neuron activity comprising: evaluation activity, communication activity and programming activity.

### Claim 15 (depends on 14)

The network of claim 14, further comprising:
a time counter that keeps track of the time elapsed since a total integrated input for the neuron exceeds a pre-determined threshold value;
wherein in the evaluation phase, evaluation activity of a neuron comprises determining if a total integrated input for the neuron exceeds a pre-determined threshold value to generate a spike, and if the integrated input exceeds the pre-determined threshold value in the evaluation phase, then the time counter is reinitialized.

### Claim 16 (depends on 15)

The network of claim 15, wherein:
in the communication phase, communication activity of a neuron comprises: if the integrated input exceeded the pre-determined threshold value in the evaluate phase, then generating a read signal on an axon for the neuron, and integrating signals received on a dendrite for the neuron.

### Claim 17 (depends on 16)

The network of claim 16, wherein:
in the programming phase, programming activity of a neuron comprises generating a signal for decreasing or increasing the resistance of a synaptic device connected between the neuron and another neuron.

### Claim 18 (depends on 13)

The network of claim 13, wherein each axon driver and each dendritic driver includes a stochastic signal generator for generating a stochastic signal based on spiking of an associated neuron.

### Claim 19 (depends on 18)

The network of claim 18, wherein each stochastic signal generator comprises:
a cyclic counter that is constantly updating its value in every programming phase;
a spike dependent counter that is initiated when an associated neuron spikes; and
a comparator that creates a binary enable pulse if the value of the spike dependent counter is greater than the value of the cyclic counter.

### Claim 20 (depends on 19)

The network of claim 19, wherein:
the interconnect circuit comprises a cross-bar array coupled to the plurality of electronic neurons to interconnect the plurality of electronic neurons; and
the time phased activity of the electronic neurons is capable of changing the state of the synaptic devices as a function of time since a last spiking of an electronic neuron firing a spiking signal.

### Claim 21 (depends on 12)

The network of claim 12 wherein each synaptic device comprises a static random access memory device.

### Claim 22

A method, comprising:
when an electronic neuron spikes, sending a spiking signal from the electronic neuron to each axon driver and each dendrite driver connected to a spiking electronic neuron in a network of electronic neurons interconnected via plural synaptic devices using axon paths, dendrite paths and membrane paths, wherein each synaptic device comprises a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, such that the drain terminal is connected in series with a first terminal of the variable state resistor;
generating a timing signal for controlling phased operation of the electronic neurons, the timing signal providing a sequence of phases, wherein activity of each electronic neuron is confined to said phases such that the synaptic devices provide spike-timing dependent plasticity based on the activity of the electronic neurons in a time phased fashion, for producing spike time dependent plasticity.

### Claim 23 (depends on 22)

The method of claim 22, wherein:
the source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path;
each variable state resistor comprises a phase change memory device;
each transistor device comprises a field effect transistor; and
wherein the source terminal of the transistor functions as an axon, the gate terminal of the transistor functions as a membrane and the second terminal of the variable state resistor functions as a dendrite.

### Claim 24 (depends on 23)

The method of claim 23, further comprising:
generating a timing signal for controlling phased operation of the electronic neurons, the timing signal providing an evaluation phase, a communication phase, a first programming phase and a second programming phase; and
controlling activity of each electronic neuron at any instant in time using the timing signal, wherein the neuron activity comprises evaluation activity, communication activity and programming activity.

### Claim 25 (depends on 24)

The method of claim 24, wherein:
in the evaluation phase, evaluation activity of a neuron comprises determining if a total integrated input for the neuron exceeds a pre-determined threshold value to generate a spike, and.
if the integrated input exceeds the pre-determined threshold value in the evaluate phase, then a time counter that keeps track of the time since a total integrated input for the neuron exceeds a pre-determined threshold value, is initialized to begin its operation of time counting.

### Claim 26 (depends on 25)

The method of claim 25, wherein:
in the communication phase, communication activity of a neuron comprises: if the integrated input exceeded the pre-determined threshold value in the evaluate phase, then generating a read signal on an axon path for the neuron, generating a bias potential on a membrane path for the neuron, and integrating signals received on a dendrite path for the neuron.

### Claim 27 (depends on 26)

The method of claim 26, wherein:
in the programming phase, programming activity of a neuron comprises generating a signal for decreasing or increasing the resistance of a variable state resistor in a synaptic device connected between the neuron and another neuron.

### Claim 28 (depends on 27)

The method of claim 27, wherein:
in the programming phase:
during a first programming interval, programming activity of a neuron comprises the neuron generating set pulse on a dendrite path for the neuron if the integrated input exceeded the pre-determined threshold value in the evaluation phase; and
during a second programming interval, programming activity of the neuron comprises the neuron generating a reset pulse on a membrane path for the neuron if the integrated input exceeded the pre-determined threshold value in the evaluate phase.

### Claim 29 (depends on 28)

The method of claim 28, wherein:
in the programming phase:
during the first programming interval, programming activity of a neuron further comprises the neuron generating an enable pulse of decreasing strength, in amplitude or probability of occurrence, on a membrane path for the neuron, as a function of the value of a time counter that keeps track of the time elapsed since said total integrated input exceeds a pre-determined threshold value.

### Claim 30 (depends on 28)

The method of claim 28, wherein:
in the programming phase:
during the second programming interval, programming activity of a neuron further comprises the neuron generating an enable pulse of decreasing strength, in amplitude or probability of occurrence, on a dendrite path for the neuron, as a function of the value of a time counter that keeps track of the time elapsed since said total integrated input exceeds a pre-determined threshold value.

### Claim 31 (depends on 30)

The method of claim 30, wherein:
interconnecting plural electronic neurons includes utilizing an interconnect circuit comprising a cross-bar array, the cross-bar array comprises:
plurality of axon paths, dendrite paths and membrane paths, such that the dendrites paths are orthogonal to the axon path and membrane paths;
such that each synaptic device is at a cross-point junction of the cross-bar array coupled between a dendrite path and an axon path, and between the dendrite path and membrane path;
wherein the time phased activity of the electronic neurons is changing the state of the variable state resistors as a function of time since a last spiking of an electronic neuron firing a spiking signal.