# US 2012/0075938 A1 · Adaptive and Dynamic Stability Enhancement for Memories

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- Number: US 2012/0075938 A1
- Document ID: US20120075938A1
- Status: Published application
- Kind: A1
- Application number: 12/888,575
- Filed: 2010-09-23
- Published: 2012-03-29
- Earliest claimed: 2010-09-23
- Assignees: Intel Corporation
- Inventors: Pramod Kolar; Fatih Hamzaoglu; Yih Wang; Eric A. Karl; Yong-Gee NG; Uddalak Bhattacharya; Kevin X. Zhang; Hyunwoo Nho
- Web page: https://patentgrep.com/patent/US20120075938A1

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

## Claims

### Claim 1

An apparatus comprising:
a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage;
a controller to receive the sensor voltage and provide a control signal based thereon; and
a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the plurality of sensors are connected in parallel to produce the sensor voltage.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the plurality of sensors produce an average voltage as the sensor voltage.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the sensors measure the voltage across cross-coupling nodes of a memory cell.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the sensors each comprise complementary pull-up and pass-gate transistors and the sensors measure the ratio of a voltage of the pull-up and the pass gate transistors.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the sensors comprise first and second inverters having connected internal nodes and wherein the sensors measure the voltage at the internal nodes.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the inverters are coupled between a source voltage and a drain voltage that are applied to cells of the plurality of memory cells.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the control signal comprises an on or off signal to a gate of the word-line under-drive circuit.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the controller compares the sensor voltage to a reference voltage to switch the control signal on or off.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the read/write assist circuit comprises a word-line under-drive circuit to reduce the drive voltage applied to a word-line of a memory cell of the plurality of memory cells in response to the control signal.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the word-line under-drive circuit comprises a word-line driver circuit and a switch controlled by the controller to reduce the voltage supplied to the word-line drive circuit.

### Claim 11 (depends on 11)

The apparatus of claim 11, wherein the switch is coupled between a power supply to the word-line drive circuit and a ground.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the switch is coupled between high and low sides of a power supply to the word-line drive circuit.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the word-line under-drive circuit receives a first control signal from the controller to cause a first switch to reduce the power supply to a word-line drive circuit and a second control signal from the controller to cause a second switch to reduce the power supply to the word-line drive circuit.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the sensors dynamically track performance variations between and among the plurality of memory cells.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the controller dynamically adjusts settings of the read/write assist circuit in response to the sensors.

### Claim 16

A method comprising:
sensing a voltage at a plurality of sensors each located near a plurality of memory;
receiving the sensor voltage at a controller and providing a control signal based thereon; and
adjusting a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

### Claim 17 (depends on 16)

The method of claim 16, further comprising comparing the sensor voltage to a reference voltage and wherein providing a control signal comprises switching the control signal on or off based on the comparison.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein adjusting a parameter comprises adjusting an amount of under-drive power of a word-line under-drive circuit in response to the control signal.

### Claim 19

An apparatus comprising:
a processing engine;
a system bus coupled to the processing engine and to an input/output hub;
a plurality of static random access memory cells in a memory array coupled to the processing engine as a cache memory;
a plurality of sensors each located near memory cells of the memory array each coupled in parallel to provide a combined sensor voltage;
an under-drive controller to receive the combined sensor voltage and to provide a control signal based thereon; and
a plurality of read/write assist circuits, each coupled to the controller and to a respective memory cell the memory array to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the read/write assist circuits comprise word-line under-drive circuits to reduce the drive voltage applied to a word-line of a memory cell of the memory array in response to the control signal.