# US 2012/0075907 A1 · Resistor structure for a non-volatile memory device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0075907 A1 - Document ID: US20120075907A1 - Status: Published application - Kind: A1 - Application number: 12/894,087 - Filed: 2010-09-29 - Published: 2012-03-29 - Earliest claimed: 2010-09-29 - Assignees: Crossbar, Inc. - Inventors: Sung Hyun JO - Web page: https://patentgrep.com/patent/US20120075907A1 ## CPC - H10D 1/47: Resistors having no potential barriers - G11C 11/22: using ferroelectric elements - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]} - G11C 13/0069: {Writing or programming circuits or methods} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/801: {Constructional details of multistable switching devices} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/841: {Electrodes} - H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)} - G11C 2213/33: Material including silicon - G11C 2213/56: Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value. ## Claims ### Claim 1 A method for programming a non-volatile resistive switching memory device, comprising: providing a switching device, the switching device comprising a first electrode, a switching material overlying the first electrode, a second electrode comprising at least a metal material overlying the switching material and a resistive material disposed between the first electrode and the switching material, the resistive material having an ohmic characteristic and being characterized by a resistance substantially the same as an on state resistance of the switching device; and applying a first voltage pulse to the switching device to cause a change of state of the switching device from a first state to a second state, the change of state being free from a time delay associated with an RC constant from a resistive element and being free from a parasitic capacitance coupled to the switching device. ### Claim 2 (depends on 1) The method of claim 1 wherein the first state is a first resistance of the switching material and the second state is a second resistance of the switching material. ### Claim 3 (depends on 1) The method of claim 1 wherein resistive material is configured to cause a programming current to be no greater than a predetermined value to flow in the switching device upon application of the first voltage pulse. ### Claim 4 (depends on 1) The method of claim 1 wherein the resistive switching device is further free from a reverse bias associated with the parasitic capacitance after the first voltage pulse, the reverse bias causes an undesirable erase cycle to the switching device. ### Claim 5 (depends on 1) The method of claim 1 wherein the resistive element is a resistor device or a transistor device. ### Claim 6 (depends on 1) The method of claim 1 wherein the on state is a low resistance state. ### Claim 7 (depends on 1) The method of claim 1 wherein the first electrode is spatially orthogonal to the second electrode. ### Claim 8 (depends on 1) The method of claim 1 wherein the resistive switching device is disposed in an interconnected crossbar array. ### Claim 9 (depends on 1) The method of claim 1 wherein the resistive switching device is free from an external circuitry for current control in a bit line or a word line to control the programming current. ### Claim 10 (depends on 9) The method of claim 9 wherein the external circuitry causes a parasitic capacitance and a parasitic RC (resistance-capacitance) time delay during programming (Read, Write, or Erase). ### Claim 11 (depends on 9) The method of claim 9 wherein the external resistor circuitry causes a reverse bias after programming and causes an undesirable erase cycle. ### Claim 12 (depends on 1) The method of claim 1 wherein the resistive material maintains the resistance upon application of the first voltage pulse. ### Claim 13 (depends on 1) The method of claim 1 wherein the resistive material is disposed between the second electrode and the switching region. ### Claim 14 (depends on 1) The method of claim 1 wherein the first electrode and the second electrode comprises at least copper, tungsten, or aluminum, the metal material comprises silver, gold, platinum, palladium, aluminum, nickel or aluminum, the switching material comprises at least an amorphous silicon material, and the resistive material comprises a dielectric material. ### Claim 15 (depends on 14) The method of claim 14 wherein the metal material forms a metal region in a portion of the switching material upon application of a positive voltage greater than a first threshold voltage to the second electrode, wherein the metal region further comprises a filament structure characterized by a length depending on an operating voltage applied to the first electrode or the second electrode. ### Claim 16 A non-volatile resistive switching memory device, comprising: a first electrode; a second electrode comprising a metal region; a switching material in direct contact with the metal region of the second electrode; a resistive material disposed between the second electrode and the switching material, the resistive material having an ohmic characteristic and having a resistance substantially the same as an on state resistance. ### Claim 17 (depends on 13) The device of claim 13 wherein the switching material is characterized by a first resistance, the first resistance depends on a voltage applied to the first electrode or the second electrode. ### Claim 18 (depends on 16) The device of claim 16 wherein the resistive material is characterized by a second resistance independence of the voltage applied to the first electrode or the second electrode. ### Claim 19 (depends on 16) The device of claim 16 wherein the resistive material forms a first interface with the switching material, the first interface is having an ohmic characteristic and free of a Schottky barrier. ### Claim 20 (depends on 16) The device of claim 16 wherein the resistive material forms a second interface with the second electrode, the second interface is having an ohmic characteristic and free of a Schottky barrier. ### Claim 21 (depends on 16) The device of claim 16 wherein the on-state resistance is a low resistance state of the switching device. ### Claim 22 (depends on 16) The device of claim 16 wherein the switching device is free of an external current compliance. ### Claim 23 (depends on 16) The device of claim 16 wherein the switching device is further characterized by an erase voltage substantially the same as a write voltage. ### Claim 24 (depends on 16) The device of claim 16 wherein the resistive material is a doped semiconductor material. ### Claim 25 (depends on 16) The device of claim 16 wherein the resistive material comprises a composite of an insulator material and a metal material, wherein the metal material is characterized by a concentration or a gradient in the insulator material, the resistance of the insulator material is adjusted by the concentration or the gradient of the metal material or a combination. ### Claim 26 (depends on 16) The device of claim 16 wherein the resistive material comprises at least a semiconductor material and a metal material, wherein the metal material is characterized by a concentration or a gradient in the resistive material, the resistance of the semiconductor material is adjusted by the concentration or the gradient of the metal material or a combination. ### Claim 27 (depends on 16) The device of claim 16 further comprises a metal material interposed between the switching material and the resistive material; the metal material prevents a non-ohmic interface between the switching material and the resistive material. ### Claim 28 An array of memory cells, comprising: at least one first structure spatially configured to extend in a first direction, each of the first structure comprising a first electrode, a resistive material overlying the first electrode, and a metal material overlying resistive material, the first structure being spatially configured to extending in a first direction; one or more switching element overlying the metal material of the first structure; and a second electrode structure overlying the each of the one or more switching element, the second electrode structure being spatially configured to extend in a second direction orthogonal to the first direction. ### Claim 29 (depends on 28) The array of memory cells of claim 28 wherein the resistive material limits an operating current to flow in each of the memory cells and wherein the array of memory cells being free of a current compliance. ### Claim 30 (depends on 28) The array of memory cells of claim 28 wherein the metal material causes an ohmic interface between the switching material and the resistive material and prevents a Schottky barrier to form from the resistive material and the switching material. ### Claim 31 (depends on 28) The array of memory cells of claim 28 further characterized by free of a current compliance ### Claim 32 An array of memory cells, comprising: one or more first electrode spatially configured to extend in a first direction, a plurality of first structures, each of the first structures comprising a resistive material overlying the first electrode, and a metal material overlying resistive material, and a switching element overlying the metal material; and a second electrode structure overlying the switching element, the second electrode structure being spatially configured to extend in a second direction orthogonal to the first direction. ### Claim 33 (depends on 32) The array of memory cells of claim 32 wherein the resistive material limits an operating current to flow in each of the memory cells and wherein the array of memory cells being free of a current compliance. ### Claim 34 (depends on 32) The array of memory cells of claim 32 wherein the metal material causes a ohmic interface between the switching material and the resistive material and prevents a Schottky barrier to form from the resistive material and the switching material ### Claim 35 A method of forming a memory device, comprising: providing a semiconductor substrate having a surface region; forming a first dielectric material overlying the surface region of the semiconductor substrate; forming a first electrode material overlying the first dielectric material; forming a resistive material overlying the first electrode material; forming a metal material overlying the resistive material; forming a switching material overlying the metal material subjecting the first electrode material the resistive material, the metal material, and the switching material to a first pattern and etch process to form a first structure , the first structure being elongated in shape and extending in a first direction; subjecting the switching material to a second pattern and etch process to form one or more switching elements overlying the metal material; forming a second electrode structure extending in a second direction spatially perpendicular to the first electrode structure overlying the one or more switching elements; and forming one or more switching device from the first electrode structure, the resistive material, the metal material, the one or more switching elements and the second electrode structure. ### Claim 36 (depends on 35) The method of claim 35 wherein the first resistive material forms a series resistor coupled to each of the one or more switching device. ### Claim 37 (depends on 36) The method of claim 36 wherein the series resistor causes a current compliance for the switching device. ### Claim 38 (depends on 35) The method of claim 35 wherein the switching material comprises an amorphous silicon material. ### Claim 39 (depends on 35) The method of claim 35 wherein the switching material further comprises a buffer material disposed between the switching material and the metal material to control an interfacial defect level. ### Claim 40 A method of forming a memory device, comprising: providing a semiconductor substrate having a surface region; forming a first dielectric material overlying the surface region of the semiconductor substrate; forming a first electrode material overlying the first dielectric material; forming a resistive material overlying the first electrode material; forming a metal material overlying the resistive material; forming a switching material overlying metal material subjecting the first electrode material the resistive material, the metal material, and the switching material to a first pattern and etch process to form a first structure , the first structure being elongated in shape and extending in a first direction; subjecting the resistive material, the metal material, and the switching material to a second pattern and etch process to form one or more switching elements and to form one or more resistor associated with the respective one or more switching element overlying the metal material; forming a second electrode structure extending in a second direction spatially perpendicular to the first electrode structure overlying at least the switching element; and forming one or more switching device from at least the first electrode structure, the one or more switching elements, the respective resistor device associated with the one or more switching element, and the second electrode structure, the one or more resistor causes a programming current in the switching element to be no greater than a predetermined current upon application of a programming voltage to the first electrode or the second electrode. ### Claim 41 (depends on 40) The method of claim 40 wherein the first resistive material forms a series resistor coupled to each of the one or more switching device. ### Claim 42 (depends on 40) The method of claim 40 wherein the series resistor causes a current compliance for the switching device. ### Claim 43 (depends on 40) The method of claim 40 wherein the switching material comprises an amorphous silicon material. ### Claim 44 (depends on 40) The method of claim 40 wherein the switching material further comprises a buffer material disposed between the switching material and the metal material to control an interfacial defect level.