# US 2012/0075136 A1 · A/d conversion device

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- Number: US 2012/0075136 A1
- Document ID: US20120075136A1
- Status: Published application
- Kind: A1
- Application number: 13/267,632
- Filed: 2011-10-06
- Published: 2012-03-29
- Earliest claimed: 2009-04-09
- Assignees: Denso Corporation; Olympus Corporation
- Inventors: Shuichi Kato
- Web page: https://patentgrep.com/patent/US20120075136A1

## CPC

- H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)}
- H03M 1/14: Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M 1/502: {using tapped delay lines}
- H03M 1/60: with intermediate conversion to frequency of pulses
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An A/D conversion device has first to third pulse delay circuits, first to third pulse passage stage detection circuits, a time output circuit, and an output circuit. Each of the first to third pulse delay circuit has multiple stages of delay units which are connected together and delay a first to a third pulse signals, respectively. Each of the first to third pulse passage stage detection circuit detects a first to a third number of stages, respectively. The time output circuit outputs a time signal. The output circuit outputs the digital value corresponding to the third number of stages.

## Claims

### Claim 1

An A/D conversion device which converts an analog input voltage to a digital value, the A/D conversion device comprising:
a first pulse delay circuit which receives a first pulse signal at a first time as input, and has multiple stages of delay units which are connected together and delay the first pulse signal for a delay period according to a magnitude of a first analog voltage;
a first pulse passage stage detection circuit which detects a first number of stages when the first pulse signal has passed through the delay unit in the first pulse delay circuit;
a second pulse delay circuit which receives a second pulse signal at a second time that is the same as the first time, and has multiple stages of delay units which are connected together and delay the second pulse signal for a delay period according to a magnitude of a second analog voltage different from the first analog voltage;
a second pulse passage stage detection circuit which detects a second number of stages when the second pulse signal has passed through a delay unit in the second pulse delay circuit;
a time output circuit which outputs a time signal indicating a time at which a difference between the first number of stages and the second number of stages becomes a predetermined number of stages;
a third pulse delay circuit which receives a third pulse signal at a third time as input, at a same time as the first time and the second time as input, and has delay units which are connected together and delay the third pulse signal for a delay period according to a magnitude of the analog input voltage;
a third pulse passage stage detection circuit which detects a third number of stages when the third pulse signal has passed through a delay unit in the third pulse delay circuit; and
an output circuit which outputs the digital value corresponding to the third number of stages detected at a time indicated by the time signal.

### Claim 2 (depends on 1)

The A/D conversion device according to claim 1, further comprising:
a memory circuit which stores a sampling time corresponding to the time indicated by the time signal,
wherein the third pulse delay circuit further receives a fourth pulse signal at a fourth time after the first time, the second time, and the third time as input,
the third pulse passage stage detection circuit further detects a fourth number of stages when the fourth pulse signal has passed through delay units in a fourth pulse delay circuit, and
the output circuit further outputs the digital value corresponding to the fourth number of stages detected at a time at which the sampling time stored in the memory circuit has elapsed after the fourth pulse signal has been input.

### Claim 3 (depends on 2)

The A/D conversion device according to claim 2, further comprising:
a control circuit which stops a operation of the first pulse delay circuit or the second pulse delay circuit after the sampling time has been stored in the memory circuit.

### Claim 4 (depends on 2)

The A/D conversion device according to claim 2, further comprising:
a control circuit which stops the operations of the first pulse delay circuit and the second pulse delay circuit after the sampling time has been stored in the memory circuit.