# US 2012/0075022 A1 · Differential amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0075022 A1 - Document ID: US20120075022A1 - Status: Published application - Kind: A1 - Application number: 12/980,340 - Filed: 2010-12-29 - Published: 2012-03-29 - Earliest claimed: 2010-09-27 - Assignees: Novatek Microelectronics Corp. - Inventors: Yung-Cheng Lin - Web page: https://patentgrep.com/patent/US20120075022A1 ## CPC - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H03F 3/45219: {Folded cascode stages} - H03F 3/45636: {by using feedback means (H03F3/45744 takes precedence)} - H03F 2203/45008: the addition of two signals being made by a resistor addition circuit for producing the common mode signal - H03F: AMPLIFIERS ## Abstract A differential amplifier includes a pair of input transistors, a pair of load transistors, a pair of impedance devices, a pair of auxiliary input transistors, and a pair of shield transistors is provided. The input transistors provide two input terminals. The load transistors provide two output terminals and two first terminals connected to first voltage. The impedance devices are coupled between the output terminals in series. The auxiliary input transistors have two control terminals respectively connected to the input terminals, two first terminals, and two second terminals. The input transistors and the auxiliary input transistors have reverse conductive type. The shield transistors has a pair of control terminals, a pair of first terminals respectively connected to the second terminals of the auxiliary input transistors and coupled to a second voltage through a pair of current sources, and a pair of second terminals respectively connected to the output terminals. ## Claims ### Claim 1 A differential amplifier, electrically coupled between a first voltage and a second voltage, comprising: a pair of input transistors, for providing a pair of input terminals; a pair of load transistors, for providing a pair of output terminals, having a pair of first terminals electrically coupled to the first voltage; a pair of impedance devices, electrically coupled between the pair of output terminals in series; a pair of auxiliary input transistors, having a pair of control terminals, a pair of first terminals, and a pair of second terminals, wherein the pair of control terminals are respectively electrically coupled to the pair of input terminals, wherein the pair of input transistors and the pair of auxiliary input transistors have reverse conductive type; and a pair of shield transistors, having a pair of control terminals, a pair of first terminals, and a pair of second terminals, wherein the pair of first terminals are respectively electrically coupled to the pair of second terminals of the pair of auxiliary input transistors and are coupled to the second voltage through a pair of current sources, wherein the pair of second terminals are respectively electrically coupled to the pair of output terminals. ### Claim 2 (depends on 1) The differential amplifier according to claim 1, wherein the first voltage and the second voltage are a combination of a system high voltage and a system low voltage, and the pair of input transistors comprises: a pair of first terminals, connected with each other, and coupled to the second voltage through a current source circuit; a pair of control terminals, respectively electrically coupled to the pair of input terminals; and a pair of second terminals, respectively electrically coupled to a pair of second terminals of the pair of load transistors as the pair of output terminals. ### Claim 3 (depends on 2) The differential amplifier according to claim 2, wherein the pair of first terminals of the pair of auxiliary input transistors is coupled to the first voltage through a current source circuit. ### Claim 4 (depends on 1) The differential amplifier according to claim 1, wherein the pair of control terminals of the pair of shield transistors is electrically coupled to an external control terminal. ### Claim 5 (depends on 1) The differential amplifier according to claim 1, wherein the pair of current sources coupled to the pair of second terminals of the pair of auxiliary input transistors is resistors or metal-oxide-semiconductor (MOS) transistors. ### Claim 6 (depends on 1) The differential amplifier according to claim 1, wherein the pair of impedance devices is constituted by resistors, a MOS transistor, or a plurality of MOS transistors that are coupled together. ### Claim 7 (depends on 1) The differential amplifier according to claim 1 further comprising a differential to single-ended conversion circuit, wherein the differential to single-ended conversion circuit receives a pair of differential voltage signals from the pair of output terminals and converts the pair of differential voltage signals into an output voltage signal. ### Claim 8 (depends on 1) The differential amplifier according to claim 1, wherein the pair of auxiliary input transistors are P-type MOS (PMOS) transistors, and the pair of input transistors are N-type MOS (NMOS) transistors. ### Claim 9 (depends on 1) The differential amplifier according to claim 1, wherein the differential amplifier is served as a comparator, and the pair of output terminals of the comparator are subsequently coupled to a pair of input terminals of a differential to single-ended conversion circuit. ### Claim 10 (depends on 9) The differential amplifier according to claim 9, wherein the differential to single-ended conversion circuit comprises: a pair of receiving transistors, having a pair of control terminals, a pair of first terminals, and a pair of second terminals, wherein the pair of control terminals are electrically coupled to the pair of output terminals of the comparator, and the pair of first terminals are coupled to a third voltage; a pair of current mirror transistors, having a pair of control terminals, a pair of second terminals, and a pair of first terminals, wherein the pair of first terminals are electrically coupled to a fourth voltage, the pair of second terminals are respectively electrically coupled to the pair of second terminals of the pair of receiving transistors, and the pair of control terminals are electrically coupled with each other; and an inverter, having two voltage control terminals, an output terminal, and an input terminal, wherein the voltage control terminals are respectively electrically coupled to the third voltage and the fourth voltage, wherein one of the pair of second terminals of the pair of receiving transistors is electrically coupled to the pair of control terminals of the pair of current mirror transistors, and another one of the pair of second terminals is electrically coupled to the input terminal of the inverter.