# US 2012/0074981 A1 · Method and apparatus for device parameter measurement

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- Number: US 2012/0074981 A1
- Document ID: US20120074981A1
- Status: Published application
- Kind: A1
- Application number: 12/892,989
- Filed: 2010-09-29
- Published: 2012-03-29
- Earliest claimed: 2010-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tseng Chin Luo; Chu Fu CHEN; Min-Tar LIU; Yuan-Yao CHANG
- Web page: https://patentgrep.com/patent/US20120074981A1

## CPC

- G01R 31/2621: {for testing field effect transistors, i.e. FET's}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor.

## Claims

### Claim 1

A device parameter test circuit comprising:
an operational amplifier having a first input at a first node, a second input at a second node, and an output at a third node, the first node being coupled to a reference voltage;
a first switch configured to selectively couple the second node to the third node;
a second switch configured to selectively couple the second node to a fourth node;
a constant current source coupled to the fourth node; and
a third switch configured to selectively couple the fourth node to a first voltage supply node;
wherein the device parameter test circuit is configured through selective triggering of the switches to measure a selected parameter from a plurality of parameters of a device coupled to the device parameter test circuit.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising a metal oxide semiconductor (MOS) transistor having a gate coupled to the third node, a source coupled to the fourth node, and a drain coupled to a second voltage supply node.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the constant current source is configured to provide a constant current that is a product of a predetermined current and a width-to-length ratio of the transistor.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the first, second, and third switches are controlled by a control signal, wherein the first and third switches are configured to be closed responsive to a first value of the control signal, and wherein the second switch is configured to be closed responsive to a second value of the control signal.

### Claim 5

A method of measuring a parameter of a device in a circuit, the method comprising:
providing a device under test (DUT) including a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node;
coupling a constant current source to the source of the transistor;
coupling an operational amplifier to the transistor; and
measuring a parameter of the transistor.

### Claim 6 (depends on 5)

The method of claim 5, wherein the operational amplifier has a first input at a first node, a second input at a second node, and an output at a third node, the output being coupled to the gate of the transistor, the first node being coupled to a reference voltage.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
providing a first switch configured to selectively couple the second node to the third node;
providing a second switch configured to selectively couple the second input of the operational amplifier to the source of the transistor;
providing a third switch configured to selectively couple the source of the transistor to a second voltage supply node;
controlling the switches to close either the first and third switches or the second switch; and
setting the reference voltage and the first voltage supply node to first and second control voltages, respectively;
wherein measuring the parameter of the transistor comprises measuring the parameter at the gate or the drain of the transistor.

### Claim 8 (depends on 7)

The method of claim 7, wherein the transistor is an NMOS transistor and controlling the switches includes closing the second switch, and wherein the measured parameter is a threshold voltage of the transistor.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first control voltage is about zero, the second control voltage is a power supply voltage, and the threshold voltage is measured in a saturation mode of the transistor.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first control voltage is about zero, the second control voltage is a substantially small voltage, and the threshold voltage is measured in a linear mode of the transistor.

### Claim 11 (depends on 7)

The method of claim 7, wherein the transistor is an NMOS transistor and controlling the switches comprises closing the first and third switches, and wherein the measured parameter is a drain current of the transistor.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first control voltage is a power supply voltage, the second control voltage is the power supply voltage, and the drain current is measured in a saturation mode of the transistor.

### Claim 13 (depends on 11)

The method of claim 11, wherein the first control voltage is about zero, the second control voltage is a power supply voltage, and the drain current is measured in a cutoff mode of the transistor.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first control voltage is a power supply voltage, the second control voltage is a substantially small voltage, and the drain current is measured in a linear mode of the transistor.

### Claim 15

A circuit comprising:
an operational amplifier having a first input at a first node, a second input at a second node, and an output at a third node, the first node being coupled to a reference voltage;
a constant current source coupled to the second node and to a first voltage supply node; and
a metal oxide semiconductor (MOS) transistor having a gate coupled to the third node, a source coupled to the second node, and a drain coupled to a second voltage supply node,
wherein the operational amplifier is provided by a first source measurement unit (SMU) comprising the operational amplifier and a measurement device configured to measure the voltage of the third node, and wherein the constant current source is provided by a second SMU.

### Claim 16 (depends on 15)

The circuit of claim 15, further comprising a third SMU configured to set the second voltage supply node to a power supply voltage, and wherein the measured output of the operational amplifier is a threshold voltage of the transistor in a saturation mode.

### Claim 17 (depends on 15)

The circuit of claim 15, further comprising a third SMU configured to set the second voltage supply node to a substantially small voltage, and wherein the measured output of the operational amplifier is a threshold voltage of the transistor in a linear mode.

### Claim 18

A circuit test system comprising:
a plurality of transistors arranged in rows and columns,
a first plurality of source measurement units (SMUs), each SMU in the first plurality of SMUs corresponding to one of the rows and comprising an operational amplifier having a first input, a second input, and an output provided at a corresponding one of a first plurality of lines, that SMU configured to measure a voltage of the corresponding said one line in the first plurality;
a second plurality of SMUs, each SMU in the second plurality of SMUs corresponding to one of the rows and configured to provide a constant current source to a corresponding one of a second plurality of lines;
a decoder configured to select one of the columns; and
a switching module configured to:
couple a gate of each transistor in the selected column to a corresponding line in the first plurality of lines, and
couple a source of each transistor in the selected column to a corresponding line in the second plurality of lines;
wherein the source of each transistor in the selected column is coupled by the switching module to the second input of the operational amplifier in a corresponding SMU in the first plurality of SMUs.

### Claim 19 (depends on 18)

The system of claim 18, wherein the transistors are NMOS transistors and a drain of each transistor in the selected column is coupled to a power supply voltage, and each SMU in the first plurality of SMUs is configured to measure a threshold voltage in a saturation mode of a corresponding transistor in the selected column.

### Claim 20 (depends on 18)

The system of claim 18, wherein the transistors are NMOS transistors and a drain of each transistor in the selected column is coupled to a common drain voltage that is a substantially small voltage, and each SMU in the first plurality of SMUs is configured to measure a threshold voltage in a linear mode of a corresponding transistor in the selected column.