# US 2012/0074595 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0074595 A1 - Document ID: US20120074595A1 - Status: Published application - Kind: A1 - Application number: 13/191,843 - Filed: 2011-07-27 - Published: 2012-03-29 - Earliest claimed: 2010-09-28 - Assignees: Samsung Electronics Co., Ltd. - Inventors: JeongOh Ha; Heungkyu Kwon; YunSeok Choi; Jong-Won Lee - Web page: https://patentgrep.com/patent/US20120074595A1 ## CPC - H10W 90/00: Package configurations - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a first substrate on which a first semiconductor chip is mounted, a second substrate spaced apart from the first substrate and on which a second semiconductor chip is mounted, first pads disposed on the first substrate, second pads disposed on the second substrate to be opposite to the first pads, and connection patterns electrically connecting the opposite first and second pads to each other, respectively. The first pads are disposed asymmetrically with respect to the central axis of the first substrate. ## Claims ### Claim 1 A semiconductor package, comprising: a first substrate; a first semiconductor chip mounted on the first substrate; a second substrate spaced apart from the first substrate; a second semiconductor chip mounted on the second substrate; first pads disposed on the first substrate; second pads disposed on the second substrate to be opposite to the first pads; and connection patterns electrically connecting the opposite first and second pads to each other, respectively, wherein the first pads are disposed asymmetrically with respect to the central axis of the first substrate. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein first pads transmitting and receiving the same signal are collectively disposed in one region of the first substrate. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein one of the first pads transmitting and receiving the same signal deviates from the one region, and the semiconductor package further comprises a redistribution pad electrically connected to the one first pad and disposed in the one region. ### Claim 4 (depends on 2) The semiconductor package of claim 2, further comprising an integrated first pad into which at least two of the first pads transmitting and receiving the same signal are integrated. ### Claim 5 (depends on 4) The semiconductor package of claim 4, wherein the integrated first pad is greater in size than each of the first pads. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the central axis of the first semiconductor chip deviates from the central axis of the first substrate. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the central axis of the second semiconductor chip deviates from the central axis of the second substrate. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the second pads are asymmetrical with respect to the central axis of the second substrate. ### Claim 9 A semiconductor package, comprising: a substrate; a semiconductor chip mounted on the substrate; and a plurality of connection patterns disposed on a first surface of the substrate, the connection patterns being disposed asymmetrically with respect to the central axis of the substrate. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein the semiconductor chip deviates from the central axis of the substrate. ### Claim 11 (depends on 9) The semiconductor package of claim 9, further comprising a plurality of pads formed on the substrate to electrically connect the semiconductor chip to the connection patterns. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein pads transmitting and receiving the same signal are collectively disposed in one region of the substrate, and connection patterns connected to the pads are also collectively disposed in the one region of the substrate. ### Claim 13 (depends on 12) The semiconductor package of claim 12, further comprising: an integrated pad into which at least two pads transmitting and receiving the same signal are integrated; and an integrated connection pattern electrically connected to the integrated pad. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the integrated connection pattern has a greater size than each of the connection patterns. ### Claim 15 A semiconductor package, comprising: a first substrate; a first semiconductor chip mounted on the first substrate; a second substrate spaced apart from the first substrate; a second semiconductor chip mounted on the second substrate; first pads disposed on the first substrate; second pads disposed on the second substrate to be opposite to the first pads; and connection patterns electrically connecting the opposite first and second pads to each other, respectively, wherein: the first pads are disposed asymmetrically with respect to the central axis of the first substrate, and first pads transmitting and receiving the same signal are collectively disposed in one region of the first substrate. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein the semiconductor package is the package of a semiconductor memory used with a memory card. ### Claim 17 (depends on 15) The semiconductor package of claim 15, wherein the semiconductor package is the package of a semiconductor memory used in an information processing system. ### Claim 18 (depends on 15) The semiconductor package of claim 15, wherein the central axis of the first semiconductor chip deviates from the central axis of the first substrate. ### Claim 19 (depends on 15) The semiconductor package of claim 15, wherein the central axis of the second semiconductor chip deviates from the central axis of the second substrate. ### Claim 20 (depends on 15) The semiconductor package of claim 15, wherein the second pads are asymmetrical with respect to the central axis of the second substrate.