# US 2012/0074582 A1 · Device with through-silicon via (tsv) and method of forming the same

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- Number: US 2012/0074582 A1
- Document ID: US20120074582A1
- Status: Published application
- Kind: A1
- Application number: 12/892,409
- Filed: 2010-09-28
- Published: 2012-03-29
- Earliest claimed: 2010-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua YU; Wen-Chih CHIOU; Ebin LIAO; Tsang-Jiuh WU
- Web page: https://patentgrep.com/patent/US20120074582A1

## CPC

- H10W 20/076: {in via holes or trenches}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

## Claims

### Claim 1

A device, comprising:
a silicon substrate;
a through-silicon via (TSV) structure passing through the silicon substrate; and
an insulation structure formed between the silicon substrate and the TSV structure,
wherein a first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the TSV structure has an interface roughness with a peak-to-valley height less than 5 nm.

### Claim 2 (depends on 1)

The device of claim 1, wherein the insulation structure comprises a first insulation layer adjacent to the silicon substrate, and a second insulation layer adjacent to the TSV structure.

### Claim 3 (depends on 2)

The device of claim 2, wherein the second insulation layer has an isotropic etching rate greater than an isotropic etching rate of the first insulation layer.

### Claim 4 (depends on 2)

The device of claim 2, wherein a third interface between the first insulation layer and the second insulation layer has an interface roughness with a peak-to-valley height greater than 10 nm.

### Claim 5 (depends on 2)

The device of claim 2, wherein the first insulation layer is an oxide layer, and the second insulation layer is an oxide layer.

### Claim 6 (depends on 1)

The device of claim 1, wherein the TSV structure comprises a copper layer.

### Claim 7 (depends on 6)

The device of claim 6, wherein the TSV structure comprises a diffusion barrier layer surrounding the copper layer.

### Claim 8 (depends on 1)

The device of claim 1, further comprising a first die electrically coupled to a first side of the silicon substrate.

### Claim 9 (depends on 8)

The device of claim 8, further comprising a second die electrically coupled to a second side of the silicon substrate, opposite to the first side of the silicon substrate.

### Claim 10

A method, comprising:
forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth;
forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening; and
forming a conductive layer on the insulation structure to fill the opening;
wherein a first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the insulation structure comprises:
performing a first deposition process to form a first insulation layer adjacent to the silicon substrate, and
performing a second deposition process to form a second insulation layer adjacent to the conductive layer;
wherein the second deposition process is different from the first deposition process.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first deposition process is a thermal oxidation process.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and a plasma-enhanced atomic layer deposition (PEALD) process.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second insulation layer has an isotropic etching rate greater than an isotropic etching rate of the first insulation layer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and a plasma-enhanced atomic layer deposition (PEALD) process.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second deposition process is a thermal oxidation process.

### Claim 17 (depends on 11)

The method of claim 11, wherein the first deposition process forms a first oxide layer adjacent to the silicon substrate and the second deposition process forms a second oxide layer adjacent to the conductive layer.

### Claim 18 (depends on 10)

The method of claim 10, wherein the step of forming a conductive layer on the insulating structure forms a copper layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the conductive layer comprises a diffusion barrier layer underlying the copper layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising forming an integrated circuit die electrically coupled to the conductive layer formed in the silicon substrate.