# US 2012/0074579 A1 · Semiconductor chip with reinforcing through-silicon-vias

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- Number: US 2012/0074579 A1
- Document ID: US20120074579A1
- Status: Published application
- Kind: A1
- Application number: 12/889,615
- Filed: 2010-09-24
- Published: 2012-03-29
- Earliest claimed: 2010-09-24
- Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
- Inventors: Michael Z. Su; Gamal Refai-Ahmed; Bryan Black
- Web page: https://patentgrep.com/patent/US20120074579A1

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 90/00: Package configurations
- H10W 72/01: {Manufacture or treatment}
- H10W 72/0198: {batch processes}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.

## Claims

### Claim 1

A method of manufacturing, comprising:
connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip; and
connecting a second end of the first thu-silicon-via to a second die seal proximate a second side of the first semiconductor chip opposite the first side.

### Claim 2 (depends on 1)

The method of claim 1, comprising electrically connecting the first die seal to ground.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first semiconductor chip comprises a electrostatic discharge diode, the method comprising electrically the first die seal to the electrostatic discharge diode.

### Claim 4 (depends on 1)

The method of claim 1, comprising connecting the first end of the first through-silicon-via to a second third die seal proximate the first side of the first semiconductor chip and the second end of the first through-silicon-via to a fourth die seal proximate the second side of the first semiconductor chip.

### Claim 5 (depends on 1)

The method of claim 1, comprising connecting the first end of a second through-silicon-via to a third die seal proximate the first side of the first semiconductor chip and the second end of the second through-silicon-via to a fourth die seal proximate the second side of the first semiconductor chip.

### Claim 6 (depends on 5)

The method of claim 5, comprising connecting a conductor member to adjacent surfaces of the first and second through-silicon-vias.

### Claim 7 (depends on 1)

The method of claim 1, comprising stacking a second semiconductor chip on the first semiconductor chip.

### Claim 8 (depends on 1)

The method of claim 1, comprising electrically connecting the first through-silicon-via to a continuity circuit on the first semiconductor chip.

### Claim 9 (depends on 1)

The method of claim 1, comprising traversing the first through-silicon-via through a gettering layer in the first semiconductor chip.

### Claim 10

A method of manufacturing, comprising:
forming a first through-silicon-via in a first semiconductor chip, the first through-silicon-via including a first end and a second end;
forming a first die seal ohmic contact with the first end of the first through-silicon-via; and
forming a second die seal in ohmic contact with the second end of the first through-silicon-via.

### Claim 11 (depends on 10)

The method of claim 10, comprising electrically connecting the first die seal to ground.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first semiconductor chip comprises an electrostatic discharge diode, the method comprising electrically the first die seal to the electrostatic discharge diode.

### Claim 13 (depends on 10)

The method of claim 10, comprising forming a third die seal on ohmic contact with the first end of the first through-silicon-via and a fourth die seal in ohmic contact with the second end of the first through-silicon-via.

### Claim 14 (depends on 10)

The method of claim 10, comprising forming a second through-silicon-via in the first semiconductor chip with a first and a second end, a third die seal in ohmic contact with the first end of the second through-silicon-via, and a fourth die seal in ohmic contact with the second end of the second through-silicon-via.

### Claim 15 (depends on 14)

The method of claim 14, comprising forming a conductor member between adjacent surfaces of the first and second through-silicon-vias.

### Claim 16 (depends on 10)

The method of claim 10, comprising stacking a second semiconductor chip on the first semiconductor chip.

### Claim 17 (depends on 10)

The method of claim 10, comprising electrically connecting the first through-silicon-via to a continuity circuit on the first semiconductor chip.

### Claim 18 (depends on 10)

The method of claim 10, comprising forming a gettering layer in the first semiconductor chip and in contact with the first through-silicon-via.

### Claim 19 (depends on 10)

The method of claim 10, wherein at least the first through-silicon-via is formed using instructions stored in a computer readable medium.

### Claim 20

An apparatus, comprising:
a first semiconductor chip having a first side and a second and opposite side and including a first die seal proximate the first side and a second die seal proximate the second side; and
a first through-silicon-via having a first end connected to the first die seal and a second end connected to the second die seal.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein the first die seal is electrically connected to ground.

### Claim 22 (depends on 20)

The apparatus of claim 20, wherein the first semiconductor chip comprises an electrostatic discharge diode electrically connected to the first die seal.

### Claim 23 (depends on 20)

The apparatus of claim 20, comprising a third die seal proximate the first side and connected to the first end of the first through-silicon-via and a fourth die seal proximate the second side and connected to the second end of the first through-silicon-via.

### Claim 24 (depends on 20)

The apparatus of claim 20, comprising a third die seal proximate the first side, a fourth die seal proximate the second side, and a second through-silicon-via having a first end connected to the third die seal and a second end connected to the fourth die seal.

### Claim 25 (depends on 24)

The apparatus of claim 24, comprising a conductor member connected to adjacent surfaces of the first and second through-silicon-vias.

### Claim 26 (depends on 20)

The apparatus of claim 20, comprising a second semiconductor chip stacked on the first semiconductor chip.

### Claim 27 (depends on 20)

The apparatus of claim 20, wherein the first semiconductor chip comprises a continuity circuit electrically connected to the first through-silicon-via.

### Claim 28 (depends on 20)

The apparatus of claim 20, comprising a gettering layer in the first semiconductor chip in contact with the first through-silicon-via.

### Claim 29

An apparatus, comprising:
a first semiconductor chip having a first side and a second and opposite side and including a first die seal proximate the first side and a second die seal proximate the second side;
a first through-silicon-via having a first end connected to the first die seal and a second end connected to the second die seal; and
wherein the apparatus is embodied in instructions stored in a computer readable medium.