# US 2012/0074564 A1 · Semiconductor device and manufacturing method of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0074564 A1 - Document ID: US20120074564A1 - Status: Published application - Kind: A1 - Application number: 13/225,693 - Filed: 2011-09-06 - Published: 2012-03-29 - Earliest claimed: 2010-09-28 - Assignees: Casio Computer Co., Ltd. - Inventors: Junji SHIOTA - Web page: https://patentgrep.com/patent/US20120074564A1 ## CPC - H10W 74/147: {the encapsulations being multilayered} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/66: Conductive materials thereof - H10W 70/69: Insulating materials thereof - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device comprises a semiconductor substrate having a connection pad, an external connection electrode provided on the semiconductor substrate to be connected to the connection pad, and a sealing film provided to cover the external connection electrode, wherein an opening is provided in the sealing film to expose a center of the upper surface of the external connection electrode, and the sealing film is provided to cover an outer peripheral part of the upper surface of the external connection electrode. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate having a connection pad; an external connection electrode provided on the semiconductor substrate to be connected to the connection pad; and a sealing film provided to cover the external connection electrode, wherein an opening is provided in the sealing film to expose a center of the upper surface of the external connection electrode, and the sealing film is provided to cover an outer peripheral part of the upper surface of the external connection electrode. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the sealing film is in the form of a single film. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein an insulating film is provided on the semiconductor substrate, a wiring line is provided on the insulating film to be connected to the connection pad, and the external connection electrode is provided on a land of the wiring line. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the upper surface of the sealing film is flat except for the opening. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the thickness of the sealing film in the outer peripheral part of the upper surface of the external connection electrode is 10 μm or less. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the opening of the sealing film and the upper surface of the external connection electrode are circular, and the diameter of the opening of the sealing film is smaller than the diameter of the upper surface of the external connection electrode by 10 μm or less. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a solder bump is provided in the opening of the sealing film and on the sealing film so that the solder bump is connected to at least the center of the upper surface of the external connection electrode. ### Claim 8 A semiconductor device manufacturing method comprising: forming a sealing film to cover a peripheral side surface and an upper surface of an external connection electrode which is formed on a semiconductor substrate to be connected to a connection pad of the semiconductor substrate; and forming an opening in the sealing film, wherein the opening is formed in the sealing film so that the opening exposes a center of the upper surface of the external connection electrode and so that the sealing film covers an outer peripheral part of the upper surface of the external connection electrode. ### Claim 9 (depends on 8) The semiconductor device manufacturing method according to claim 8, wherein the sealing film is formed into a single film. ### Claim 10 (depends on 8) The semiconductor device manufacturing method according to claim 8, wherein the external connection electrode is formed by electrolytic plating using a plating resist film formed on the semiconductor substrate, and the plating resist film on the semiconductor substrate is detached, wherein after the formation of the external connection electrode, the upper part of the external connection electrode and the upper side of the plating resist film are cut off with the plating resist film remaining on the semiconductor substrate before the detachment of the plating resist film. ### Claim 11 (depends on 10) The semiconductor device manufacturing method according to claim 10, wherein after the upper part of the external connection electrode is cut off by a surface planer, the sealing film is formed to cover the entire upper surface of the external connection electrode, and before the opening is formed in the sealing film, the sealing film is formed so that the sealing film remains on the entire upper surface of the external connection electrode. ### Claim 12 (depends on 11) The semiconductor device manufacturing method according to claim 11, wherein the upper part of the external connection electrode and the upper side of the plating resist film are cut by the surface planer and simultaneously removed. ### Claim 13 (depends on 8) The semiconductor device manufacturing method according to claim 8, wherein after the formation of the sealing film, the upper side of the plating resist film is ground so that the sealing film remains 10 μm or less in thickness on the external connection electrode before the formation of the opening in the sealing film. ### Claim 14 (depends on 8) The semiconductor device manufacturing method according to claim 8, wherein the opening is formed in the sealing film by laser processing which applies a laser beam. ### Claim 15 (depends on 8) The semiconductor device manufacturing method according to claim 8, wherein the opening of the sealing film and the upper surface of the external connection electrode are circular, and the opening is formed in the sealing film so that the diameter of the opening of the sealing film is smaller than the diameter of the external connection electrode by 10 μm or less. ### Claim 16 (depends on 8) The semiconductor device manufacturing method according to claim 8, wherein a solder bump is formed in the opening of the sealing film and on the sealing film so that this solder bump is connected to at least the center of the upper surface of the external connection electrode.