# US 2012/0074558 A1 · Circuit Board Packaged with Die through Surface Mount Technology

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- Number: US 2012/0074558 A1
- Document ID: US20120074558A1
- Status: Published application
- Kind: A1
- Application number: 13/041,711
- Filed: 2011-03-07
- Published: 2012-03-29
- Earliest claimed: 2010-09-29
- Assignees: Mao Bang Electronic Co., Ltd.
- Inventors: Hsuan Yu LU; Tse Ming CHU; Kuei-Wu CHU
- Web page: https://patentgrep.com/patent/US20120074558A1

## CPC

- H10W 70/635: {Through-vias}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

## Claims

### Claim 1

A circuit board packaged with a die through surface mount technology (SMT), comprising:
a circuit board, said circuit board having a circuit layout layer on a first surface of said circuit board; and
a die, said die being connected with said circuit board on said first surface of said circuit board, said die having an input/output (I/O) point on a surface of said die, said die having a connecting wire layer on said surface of said die having said I/O point, said connecting wire layer having a plurality of pads, said pads being connected with said circuit layout layer,
wherein said die is packaged on said circuit layout layer of said circuit board through SMT with coordination of said pads.

### Claim 2 (depends on 1)

The circuit board according to claim 1,
wherein said circuit board has a second circuit layout layer on a second surface of said circuit board; and
wherein said second circuit layout layer has a plurality of connecting materials.

### Claim 3 (depends on 2)

The circuit board according to claim 2,
wherein said connecting materials are tin balls.

### Claim 4 (depends on 1)

The circuit board according to claim 1,
wherein said die is a double-data-rate (DDR) chip.

### Claim 5 (depends on 1)

The circuit board according to claim 1,
wherein said die is covered with a shell on an outside surface of said die; and
wherein said pads are exposed out of said shell.

### Claim 6 (depends on 1)

The circuit board according to claim 1,
wherein said pads are tin balls.