# US 2012/0074539 A1 · Device and methods for electrostatic discharge protection

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- Number: US 2012/0074539 A1
- Document ID: US20120074539A1
- Status: Published application
- Kind: A1
- Application number: 13/076,269
- Filed: 2011-03-30
- Published: 2012-03-29
- Earliest claimed: 2010-04-02
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Ta Lee Yu; Chi Kang Liu; Jing Liu
- Web page: https://patentgrep.com/patent/US20120074539A1

## CPC

- H10D 89/611: {using diodes as protective elements}
- H10W 72/90: Bond pads, in general
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

## Claims

### Claim 1

An electrostatic discharge protective device, the device comprising:
a semiconductor substrate;
a first N well region provided in the semiconductor substrate, the first N well region comprising:
a first heavily doped P+ region and a first heavily doped N+ region, the first heavily doped N+ region being coupled to a Vdd potential;
a first spacing between the first heavily doped P+ region and the first heavily doped N+ region, the spacing being a portion of the first N well region;
a second N well region provided in the semiconductor substrate, the second N well region comprising:
a second heavily doped P+ region and a second heavily doped N+ region;
a second spacing between the second heavily doped P+ region and the second heavily doped N+ region, the second spacing being a portion of the second N well region;
a plurality of third N well regions, one of the plurality of third N well regions being disposed between the first and second N well regions at a spacing and comprising:
a third heavily doped P+ region and a third heavily doped N+ region, the third heavily doped N+ region being electrically coupled to the first heavily coped P+ region, and the third heavily doped P+ region being electrically coupled to the second heavily doped N+ region;
a third spacing between the third heavily doped P+ region and the third heavily doped N+ region, the third spacing being a portion of the third N well region; and
a P well region provided in the semiconductor substrate abutting the second N well region; the P well region comprises:
a fourth heavily doped P+ region and a fourth heavily doped N+ region, the fourth heavily doped P+ region being coupled to a Vss potential, the fourth heavily doped N+ region being coupled to the second heavily doped P+ region in common with an input/output pad of an integrated circuit;
a fourth spacing between the fourth heavily doped P+ region and the fourth heavily doped N+ region, the fourth spacing being a portion of the P well region;
wherein a capacitance between the input/output pad and the first heavily doped N+ region or between the input/output pad and the fourth heavily doped P+ region is less than 0.1 pF.

### Claim 2 (depends on 1)

The device of claim 1 wherein the plurality of third N well regions comprise at least two N well regions.

### Claim 3 (depends on 1)

The device of claim 1 wherein the first N well region, the second N well region, and the plurality of third well regions are implanted using arsenic.

### Claim 4 (depends on 1)

The device of claim 1 wherein the first heavily doped P+ region, the second heavily doped P+ region, and the third P+ region are implanted using boron.

### Claim 5 (depends on 1)

The device of claim 1 wherein the first heavily doped N+ region, the second heavily doped N+ region, and the third heavily doped N+ region are implanted using arsenic.

### Claim 6 (depends on 1)

The device of claim 1 wherein the first heavily doped N+ region and the second heavily doped N+ region are formed by ion implantation process using arsenic.

### Claim 7 (depends on 1)

The device of claim 1 wherein the first heavily doped P+ region and the second heavily doped P+ region are formed by ion implantation process using boron as an impurity.

### Claim 8

An electrostatic discharge protective device, the device comprising:
a semiconductor substrate;
a first region and a second region in the semiconductor substrate;
a spacing between the first region and the second region, the spacing being a portion of the semiconductor substrate;
a first N well region provided in the first region, the first N well region comprising:
a first heavily doped P+ region and a first heavily doped N+ region, the first heavily doped N+ region being coupled to a Vdd potential;
a first spacing between the first heavily doped P+ region and the first heavily doped N+ region, the first spacing being a portion of the first N well region;
a second N well region provided in the first region, the second N well region comprising:
a second heavily doped P+ region and a second heavily doped N+ region, the second heavily doped N+ region being electrically couple to the first P+ region;
a second spacing between the second heavily doped P+ region and the second heavily doped N+ region, the second spacing being a portion of the second N well region;
a plurality of third N well regions in the first region, one of the plurality of third N well regions being disposed between the first and second N well regions and comprising:
a third heavily doped P+ region and a third heavily doped N+ region, the third heavily doped N+ region being electrically coupled to the first heavily doped P+ region, and the third heavily doped P+ region being electrically coupled to the second heavily doped N+ region;
a third spacing between the third heavily doped P+ region and the third heavily doped N+ region, the third spacing being a portion of the third N well region;
a fourth N well region provided in the second region, the fourth N well region comprising:
a fourth heavily doped N+ region, the fourth heavily doped N+ region being electrically coupled to the second heavily doped P+ region in common with an input/output pad of an internal circuit; and
a P well region provided in the second region abutting the fourth N well region, the P well region comprising:
a fourth heavily doped P+ region, the fourth heavily doped P+ region being coupled to a Vss potential;
wherein:
each of the plurality of third N well regions is spaced apart from an adjacent third N well region including the first and second N well regions at a spacing length, the spacing length being a portion of the first region, and
a capacitance between the input/output pad and the first heavily doped N+ region or between the input/output pad and the fourth heavily doped P+ region is less than 0.1 pF.

### Claim 9 (depends on 8)

The device of claim 8. wherein the plurality of third N well regions comprise at least two N well regions.

### Claim 10 (depends on 8)

The device of claim 8 wherein the first N well region, the second N well region, and the plurality of third N well regions are implanted using arsenic or phosphorus or antimony as implant impurity.

### Claim 11 (depends on 8)

The device of claim 8 wherein the first heavily doped P+ region and the second heavily doped P+ region are formed using ion implantation process or diffusion process to incorporate boron.

### Claim 12 (depends on 8)

The device of claim 8 wherein the first heavily doped N+ region and the second heavily doped N+ region are formed by ion implantation process using arsenic, or phosphorus, or antimony.

### Claim 13 (depends on 8)

The device of claim 8 wherein the P well region is formed using ion implantation process or diffusion process.

### Claim 14 (depends on 8)

The device of claim 8 wherein the P well region is formed by ion implantation process using boron as an impurity.

### Claim 15

An electrostatic discharge protective device, the device comprising:
a first terminal for coupling to a contact pad of an integrated circuit;
a second terminal for coupling to a power supply of the integrated circuit;
a third terminal for coupling to a ground of the integrated circuit;
a first plurality of diode devices serially coupled between the first terminal and the second terminal, the first plurality of diode devices being configured to be reverse biased;
a second plurality of diode devices serially coupled between the first terminal and the third terminal, the second plurality of diode devices being configured to be reverse biased;
wherein a capacitance between the first and the second terminals is configured to be smaller than 0.1 pF.

### Claim 16 (depends on 15)

The device of claim 15 wherein a capacitance between the first and the third terminals is configured to be smaller than 0.1 pF.

### Claim 17 (depends on 15)

The device of claim 15 wherein the first plurality of diode devices comprise one or more diode devices having a p+ region adjacent to an n-well region.

### Claim 18 (depends on 15)

The device of claim 15 wherein the first plurality of diode devices comprise two or more diode devices having a p+ region adjacent to an n-well region.

### Claim 19 (depends on 15)

The device of claim 15 wherein the second plurality of diode devices comprise one or more diode devices having an n+ region adjacent to a p-well region.

### Claim 20 (depends on 15)

The device of claim 15 wherein the second plurality of diode devices comprise two or more diode devices having an n-well region adjacent to a p-well region.