# US 2012/0074530 A1 · Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer

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- Number: US 2012/0074530 A1
- Document ID: US20120074530A1
- Status: Published application
- Kind: A1
- Application number: 13/299,808
- Filed: 2011-11-18
- Published: 2012-03-29
- Earliest claimed: 2005-07-14
- Inventors: Chang-Hyun KIM; Kyung-Ho Kim
- Web page: https://patentgrep.com/patent/US20120074530A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10W 72/536: {the connected ends being ball-shaped}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

## Claims

### Claim 1

An interposer of a semiconductor device comprising:
a semiconductor substrate including a void; and
a metal interconnect provided within the void of the semiconductor substrate, thereby forming an insulating air gap to insulate the metal interconnect.

### Claim 2 (depends on 1)

A multi-chip package comprising:
the interposer according to claim 1;
wherein at least one contact element is formed on one side of the metal interconnect to electrically connect the metal interconnect to a semiconductor integrated circuit, and the semiconductor substrate is attached to the at least one contact element; and
a plurality of semiconductor integrated circuits each including a circuit unit having internal elements, and a pad for connecting the circuit unit to the at least one contact element of the interposer,
wherein the interposer is bonded to the plurality of semiconductor integrated circuits, and connected to the circuit units of respective semiconductor integrated circuits via the at least one contact element.

### Claim 3 (depends on 2)

The multi-chip package of claim 2, wherein the metal interconnect is maintained within the air gap using the contact element.

### Claim 4 (depends on 2)

The multi-chip package of claim 2, wherein each of the semiconductor integrated circuits has no internal metal interconnect for electrical connection of internal elements.

### Claim 5 (depends on 2)

The multi-chip package of claim 2, wherein an area of the interposer is equal to the sum of areas of the semiconductor integrated circuits.

### Claim 6 (depends on 5)

The multi-chip package of claim 5, wherein the interposer further comprises an external pad to connect to a printed circuit board, which is connected to the printed circuit board via a bonding element.

### Claim 7 (depends on 2)

The multi-chip package of claim 2, wherein the area of the interposer is larger than the sum of areas of the semiconductor integrated circuits.

### Claim 8 (depends on 7)

The multi-chip package of claim 7, wherein the interposer further comprises an external pad to be connected to a printed circuit board, and the external pad is disposed on a portion of the interposer other than an area of the interposer bonded to the semiconductor integrated circuit and is connected to the printed circuit board via a bonding element.

### Claim 9 (depends on 2)

The multi-chip package of claim 2, wherein the metal interconnect is fabricated using a micro electro mechanical system (MEMS).