# US 2012/0074495 A1 · Series FinFET Implementation Schemes

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- Number: US 2012/0074495 A1
- Document ID: US20120074495A1
- Status: Published application
- Kind: A1
- Application number: 12/890,084
- Filed: 2010-09-24
- Published: 2012-03-29
- Earliest claimed: 2010-09-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chiung-Ting Ou; Chih-Chiang Chang
- Web page: https://patentgrep.com/patent/US20120074495A1

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device includes a first semiconductor fin, and a second semiconductor fin parallel to the first semiconductor fin. A straight gate electrode is formed over the first and the second semiconductor fins, and forms a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type. A first electrical connection is formed on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET.

## Claims

### Claim 1

A device comprising:
a first semiconductor fin;
a second semiconductor fin parallel to the first semiconductor fin;
a straight gate electrode over the first and the second semiconductor fins, and forming a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type; and
a first electrical connection on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first electrical connection has a longitudinal direction parallel to a longitudinal direction of the straight gate electrode.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first and the second FinFETs are n-type FinFETs.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first and the second FinFETs are p-type FinFETs.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first and the second FinFETs form a series FinFET, with second source/drain regions of the first and the second FinFETs being source/drain regions of the series FinFET.

### Claim 6 (depends on 1)

The device of claim 1 further comprising:
a third semiconductor fin parallel to the first and the second semiconductor fins, wherein the straight gate electrode extends over the third semiconductor fin to form a third FinFET of the same conductivity type as the first and the second FinFETs; and
a second electrical connection connecting the second source/drain of the second FinFET to a second source/drain of the third FinFET, wherein a first source/drain of the third FinFET is not connected to the second source/drain of the first FinFET.

### Claim 7 (depends on 6)

The device of claim 6, wherein the first, the second, and the third FinFETs form a series FinFET.

### Claim 8 (depends on 1)

The device of claim 1, wherein the first electrical connection comprises:
a first contact plug directly over and connected to the first source/drain region of the first FinFET;
a second contact plug directly over and connected to the first source/drain region of the second FinFET; and
a metal line over and connected to the first and the second contact plugs.

### Claim 9

A device comprising:
a series fin field-effect transistor (FinFET) comprising:
a first semiconductor fin;
a second semiconductor fin parallel to the first semiconductor fin, wherein outer boundaries of the first and the second semiconductor fin define a first rectangular region in a top view of the series FinFET;
a first and a second gate dielectric on top surfaces and sidewalls of the first and the second semiconductor fins;
a gate electrode over the first and the second semiconductor fins and separated from the first and the second semiconductor fins by the first and the second gate dielectrics, respectively; and
a first electrical connection on a side of the gate electrode and interconnecting portions of the first and the second semiconductor fins not covered by the gate electrode.

### Claim 10 (depends on 9)

The device of claim 9, wherein portions of the first and the second semiconductor fins directly underlying the first and the second gate electrodes, respectively, are of a same conductivity type.

### Claim 11 (depends on 9)

The device of claim 9, wherein the first electrical connection is parallel to the gate electrode.

### Claim 12 (depends on 9)

The device of claim 9, wherein the series FinFET is an n-type FinFET.

### Claim 13 (depends on 9)

The device of claim 9, wherein the series FinFET is a p-type FinFET.

### Claim 14 (depends on 9)

The device of claim 9, wherein the series FinFET further comprises:
a third semiconductor fin parallel to the first and the second semiconductor fins, wherein the first and the third semiconductor fins are on opposite sides of the second semiconductor fin, and wherein outer boundaries of the first and the third semiconductor fin define a second rectangular region comprising the first rectangular region therein; and
a second electrical connection interconnecting portions of the second and the third semiconductor fins not covered by the gate electrode, wherein the first and the second electrical connections are on opposite sides of the gate electrode.

### Claim 15

A device comprising:
a series fin field-effect transistor (FinFET) comprising:
a first, a second, and a third semiconductor fin parallel to each other; and
a straight gate electrode perpendicular to the first, the second, and the third semiconductor fins, and forming a first, a second, and a third FinFET of a same conductivity type with the first, the second, and the third semiconductor fins, respectively;
a first electrical connection on a first side of the straight gate electrode and interconnecting a first source/drain of the first FinFET to a first source/drain of the second FinFET; and
a second electrical connection on a second side of the straight gate electrode and connecting a second source/drain of the second FinFET to a second source/drain of the third FinFET.

### Claim 16 (depends on 15)

The device of claim 15, wherein no direct metal connection connects a second source/drain of the first FinFET to a first source/drain region of the third FinFET.

### Claim 17 (depends on 15)

The device of claim 15, wherein each of the first and the second electrical connections comprises a butted contact plug.

### Claim 18 (depends on 15)

The device of claim 15, wherein the first, the second, and the third FinFETs are n-type FinFETs.

### Claim 19 (depends on 15)

The device of claim 15, wherein the first, the second, and the third FinFETs are p-type FinFETs.

### Claim 20 (depends on 15)

The device of claim 15, wherein the first and the second electrical connections are parallel to the gate electrode.