# US 2012/0074492 A1 · Method of Fabricating A Semicoductor Device Having A Lateral Double Diffused Mosfet Transistor with a Lightly Doped Source and a CMOS Transistor

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- Number: US 2012/0074492 A1
- Document ID: US20120074492A1
- Status: Published application
- Kind: A1
- Application number: 13/311,400
- Filed: 2011-12-05
- Published: 2012-03-29
- Earliest claimed: 2006-03-02
- Assignees: Volterra Semiconductor Corporation
- Inventors: Budong Yu; Marco A. Zuniga
- Web page: https://patentgrep.com/patent/US20120074492A1

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/835: {comprising LDMOS}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.

## Claims

### Claim 1

A device comprising:
a laterally diffused metal oxide semiconductor (LDMOS) transistor on a substrate, the LDMOS transistor including a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, a first gate between the first drain and the first source, and a first lightly n-doped region in the first source that overlaps the first source-side n+ region and extends beneath the first gate but not the first drain; and
an n-type complementary metal oxide semiconductor (CMOS) transistor on the substrate, the n-type CMOS transistor including a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, a second gate between the second drain and the second source, and a second lightly n-doped region in the second drain that overlaps the second drain-side n+ region and extends beneath the second gate.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first drain-side n+ region, the first source-side n+ region, the second drain-side n+ region, and the second source-side n+ region are simultaneously implanted.

### Claim 3 (depends on 1)

The device of claim 1, further comprising a p-type CMOS transistor on the substrate, the p-type CMOS transistor including a third drain having a first drain-side p+ region, a third source having a second source-side p+ region, and a third gate between the third drain and the third source.

### Claim 4 (depends on 3)

The device of claim 3, wherein the first source-side p+ region, the first drain-side p+ region, and the second source-side p+ region are simultaneously implanted.

### Claim 5 (depends on 3)

The device of claim 3, further comprising:
a PMOS transistor on the substrate that includes a fourth drain having a second drain-side p+ region, a fourth source having a third source-side p+ region, and a fourth gate between the fourth drain and the fourth source; and
a NMOS transistor on the substrate that includes a fifth drain having a third drain-side n+ region, a fifth source having a third source-side n+ region, and a fifth gate between the fifth drain and the fifth source.

### Claim 6 (depends on 5)

The device of claim 5, wherein the third drain-side n+ region and the third source-side n+ region are formed at a same time as the first drain-side n+ region and the first source-side n+ region of the LDMOS transistor and the second drain-side n+ region and the second source-side n+ region of the n-type CMOS transistor.

### Claim 7 (depends on 5)

The device of claim 5, wherein the second drain-side p+ region and the third source-side p+ region are formed at the same time as the first source-side p+ region of the LDMOS transistor and the first drain-side p+ region and the second source-side p+ region of the p-type CMOS transistor.

### Claim 8 (depends on 2)

The device of claim 2, further comprising a gate oxide for each of the LDMOS transistor and the n-type CMOS transistor having a uniform gate oxide thickness between the LDMOS transistor and the n-type CMOS transistor.

### Claim 9 (depends on 8)

The device of claim 8, further comprising oxide spacers, wherein the first lightly n-doped region in the first source and the second lightly n-doped region in the second drain are formed prior to forming the oxide spacers, and the first drain-side n+ region, the first source-side n+ region, the second drain-side n+ region, and the second source-side n+ region are formed after forming the oxide spacers.

### Claim 10 (depends on 1)

The device of claim 1, further comprising a gate oxide for each of the LDMOS transistor and the n-type CMOS transistor, wherein a gate oxide thickness for the LDMOS transistor is different from that of the n-type CMOS transistor.

### Claim 11 (depends on 1)

The device of claim 1, wherein the first lightly n-doped region is implanted only in the first source and not in the first drain.

### Claim 12 (depends on 1)

The device of claim 1, wherein the first lightly n-doped region and the second lightly n-doped region are formed by simultaneous implantation that yields a same dopant concentration for the first lightly n-doped region and the second lightly n-doped region.

### Claim 13

A method of fabricating a semiconductor device, the method comprising:
forming a n-well in a surface area of a substrate;
forming a source including implanting a p-body in the n-well, a p+ region within the p-body, a first n+ region within the p-body and abutting the p+ region, the first n+ region on a side of the p+ region closer to a gate, and a lightly doped region that overlaps at least a portion of the first n+ region, the lightly doped region implanted only in the source;
forming a drain including forming a second n+ region in the drain; and
forming the gate between the source and the drain including forming the gate above a portion of the lightly doped region such that the lightly doped region extends laterally beneath a portion of the gate.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the drain includes forming a shallow drain region that surrounds the second n+ region and extends laterally beneath a portion of the gate, the second n+ region formed deeper than the shallow drain region.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the shallow drain region includes forming the shallow drain region with a concentration different than that of the lightly doped region.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
forming a gate oxide between the source and the drain;
forming an oxide spacer on both sides of the gate oxide after implanting the lightly doped region; and
forming the first n+ region and the second n+ region after forming the oxide spacer.

### Claim 17 (depends on 16)

The method of claim 16, wherein implanting the lightly doped region includes implanting the lightly doped region shallower than the first n+ region.

### Claim 18

A method of fabricating a semiconductor device, the method comprising:
implanting, into a surface of the substrate, a high voltage n-doped n-well;
forming a gate oxide in a gate region;
covering the gate oxide with a conductive material;
implanting, into a source region, a p-doped p-body;
implanting, only into the source region, a n-doped lightly doped source;
implanting, into the source region, a first n-doped n+ region, the first n-doped n+ region overlapping a portion of the n-doped lightly doped source;
implanting, into a drain region, a second n-doped n+ region; and
implanting, into the source region, a p-doped p+ region.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming an oxide spacer on each side of the gate oxide after implanting the n-doped lightly doped source but before the first n-doped n+ region and the second n-doped n+ region.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the oxide spacer is performed prior to forming the first n-doped n+ region and the second n-doped n+ region.

### Claim 21 (depends on 18)

The method of claim 18, wherein implanting the p-doped p-body is performed after forming the gate oxide.

### Claim 22 (depends on 18)

The method of claim 18, wherein forming the gate oxide includes forming a dual gate having a first gate region and a second gate region.

### Claim 23 (depends on 22)

The method of claim 22, wherein forming the dual gate includes forming a controlled gate in the first gate region that receives a signal to activate the semiconductor device, and a floating gate in the second gate region.

### Claim 24 (depends on 22)

The method of claim 22, wherein forming the n-doped lightly doped source includes forming the n-doped lightly doped source that is self-aligned to the first gate region and does not extend laterally into the second gate region as measured along a surface of the semiconductor device.

### Claim 25 (depends on 22)

The method of claim 22, wherein the first gate region includes a first conductive layer and a first oxide layer, and the second gate region includes a second conductive layer and a second oxide layer.

### Claim 26 (depends on 25)

The method of claim 25, wherein the second oxide layer is greater in thickness than the first oxide layer.

### Claim 27 (depends on 25)

The method of claim 25, wherein the first gate region abuts the second gate region.