# US 2012/0074488 A1 · Vertical transistor with hardening implatation

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- Number: US 2012/0074488 A1
- Document ID: US20120074488A1
- Status: Published application
- Kind: A1
- Application number: 12/891,966
- Filed: 2010-09-28
- Published: 2012-03-29
- Earliest claimed: 2010-09-28
- Assignees: Seagate Technology LLC
- Inventors: Young Pil Kim; Hyung-Kyu Lee; Peter Nicholas Manos; Chulmin Jung; Maroun Georges Khoury; Dadi Setiadi
- Web page: https://patentgrep.com/patent/US20120074488A1

## CPC

- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10N 70/253: {having three or more electrodes, e.g. transistor-like devices}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

## Claims

### Claim 1

A method comprising:
providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface;
implanting a hardening species into the vertical pillar transistor top surface;
oxidizing the vertical pillar transistor side surface to form a side surface oxide layer; and
removing the side surface oxide layer to form vertical pillar transistor having rounded side surfaces.

### Claim 2 (depends on 1)

The method according to claim 1 wherein the top surface is substantially planar.

### Claim 3 (depends on 1)

The method according to claim 1 wherein the hardening species is nitrogen.

### Claim 4 (depends on 1)

The method according to claim 1 wherein the removing step selectively removes the side surface oxide layer.

### Claim 5 (depends on 1)

The method according to claim 1 wherein the top surface is a parallel with the major surface of the semiconductor wafer.

### Claim 6 (depends on 1)

The method according to claim 1 wherein the top surface and the rounded side surfaces form a sharp edge.

### Claim 7 (depends on 1)

The method according to claim 1 further comprising a memory cell in electrical connection with the vertical pillar transistor.

### Claim 8 (depends on 7)

The method according to claim 7 wherein the memory cell comprises an RRAM memory cell or a spin-torque transfer memory cell.

### Claim 9 (depends on 7)

The method according to claim 7 wherein the memory cell comprise an array of memory cells.

### Claim 10 (depends on 1)

The method according to claim 1 further comprising forming a gate oxide layer on the rounded side surfaces.

### Claim 11

A method comprising:
providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface;
implanting a hardening species into the vertical pillar transistor top surface;
oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is different than the side surface oxide material layer; and
removing selectively the side surface oxide material layer to form vertical pillar transistor having rounded side surfaces and the top surfaces oxide material layer.

### Claim 12 (depends on 11)

The method according to claim 11 wherein the hardening species is nitrogen.

### Claim 13 (depends on 11)

The method according to claim 11 wherein the top surface is a parallel with the major surface of the semiconductor wafer.

### Claim 14 (depends on 11)

The method according to claim 11 wherein the top surface and the rounded side surfaces form a sharp edge.

### Claim 15 (depends on 11)

The method according to claim 11 further comprising a memory cell in electrical connection with the vertical pillar transistor.

### Claim 16 (depends on 15)

The method according to claim 15 wherein the memory cell comprises a spin-torque transfer memory cell.

### Claim 17 (depends on 15)

The method according to claim 15 wherein the memory cell comprise an array of memory cells.

### Claim 18 (depends on 11)

The method according to claim 11 further comprising forming a gate oxide layer on the rounded side surfaces.

### Claim 19

A method comprising:
providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer, each pillar structure forming a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface, the vertical pillar transistor having a drain, source and channel regions vertically stacked on top of each other and extending away from the semiconductor wafer;
implanting a hardening species into the vertical pillar transistor top surface and not into the vertical pillar transistor side surface;
oxidizing the vertical pillar transistor forming a top surfaces oxide material layer and a side surface oxide material layer, wherein the top surfaces oxide material layer is different than the side surface oxide material layer;
removing selectively the side surface oxide material layer to form vertical pillar transistor having rounded side surfaces and the top surfaces oxide material layer; and
electrically coupling a memory cell with the vertical pillar transistor.

### Claim 20 (depends on 19)

The method according to claim 19 wherein the vertical pillar transistor separated the memory cell from the semiconductor wafer.

### Claim 21

An apparatus comprising:
a vertical pillar transistor extending orthogonally from a semiconductor wafer, the vertical pillar transistor comprising a planar top surface and rounded side surfaces, the rounded side surfaces are orthogonal to the planar top surface, wherein the top surface includes a hardening implant species;
an electrically conductive gate material layer on the rounded side surfaces; and
a memory cell in electrical connection with the vertical pillar transistor.

### Claim 22 (depends on 21)

The apparatus according to claim 21 wherein the memory cell is a STRAM memory cell.

### Claim 23 (depends on 21)

The apparatus according to claim 21 wherein the memory cell is electrically between the vertical pillar transistor and the semiconductor wafer.

### Claim 24 (depends on 21)

The apparatus according to claim 21 wherein the vertical pillar transistor is electrically between the memory cell and the semiconductor wafer.

### Claim 25 (depends on 21)

The apparatus according to claim 21 further comprising a gate oxide layer between the rounded side surfaces and the electrically conductive gate material layer.

### Claim 26 (depends on 21)

The apparatus according to claim 21 further comprising a plurality of vertical pillar transistor extending orthogonally from a semiconductor wafer, wherein at least selected vertical pillar transistors comprise a planar top surface and rounded side surfaces, the rounded side surfaces are orthogonal to the planar top surface, wherein the top surface includes a hardening implant species., and an electrically conductive gate material layer is on the rounded side surfaces, and a plurality of memory cells forming a memory array, where each memory cell is in electrical connection with a selected vertical pillar transistor.