# US 2012/0074469 A1 · Asymmetric wedge jfet, related method and design structure

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- Number: US 2012/0074469 A1
- Document ID: US20120074469A1
- Status: Published application
- Kind: A1
- Application number: 12/888,828
- Filed: 2010-09-23
- Published: 2012-03-29
- Earliest claimed: 2010-09-23
- Assignees: International Business Machines Corporation
- Inventors: Xuefeng Liu; Richard A. Phelps; Robert M. Rassel; Xiaowei Tian
- Web page: https://patentgrep.com/patent/US20120074469A1

## CPC

- H10D 30/00: Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00)
- G06F 30/00: Computer-aided design [CAD]
- H10D 30/0512: {of FETs having PN homojunction gates}
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

## Claims

### Claim 1

A junction field effect transistor (JFET) having an upper surface, the JFET comprising:
a source region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the source region having an inner edge and an outer edge;
a drain region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the drain region having an inner edge and an outer edge;
a channel region disposed under the source region and the drain region; and
a shallow trench isolation (STI) region comprising an insulator material, the STI region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the STI region extending from the inner edge of the source region to the inner edge of the drain region.

### Claim 2 (depends on 1)

The JFET of claim 1, further comprising an implantation layer within the channel region, the implantation layer positioned only under the source region, and wherein the implantation layer is doped.

### Claim 3 (depends on 2)

The JFET of claim 2, wherein the channel region includes dopants and the implantation layer includes a higher concentration of dopants than the channel region.

### Claim 4 (depends on 2)

The JFET of claim 2, wherein the concentration of dopants in the implantation layer is in the range of approximately 1E15 atoms/cm3 to approximately 1E21 atoms/cm3.

### Claim 5 (depends on 1)

The JFET of claim 1, further comprising a quasi-buried upper gate in the channel region, the quasi-buried gate positioned partially under the STI region, wherein the quasi-buried upper gate does not extend under a portion of the STI region proximate to the drain region.

### Claim 6 (depends on 5)

The JFET of claim 5, wherein the quasi-buried upper gate extends at least partially along a substantially vertical sidewall of the STI region proximate to the source region.

### Claim 7 (depends on 5)

The JFET of claim 5, further comprising a quasi-buried upper gate contact to the quasi-buried upper gate, wherein the quasi-buried upper gate contact has a higher concentration of dopants than the source region.

### Claim 8 (depends on 5)

The JFET of claim 5, further comprising an implantation layer within the channel region, the implantation layer positioned only under the source region, and wherein the implantation layer includes n-type dopants.

### Claim 9 (depends on 8)

The JFET of claim 8, wherein the channel region includes n-type dopants and the implantation layer has a higher concentration of n-type dopants than the channel region.

### Claim 10

A method of forming a junction field effect transistor (JFET), the method comprising:
forming a trench in the substrate, the trench having a substantially horizontal bottom surface, a substantially vertical first side and a substantially vertical second side;
forming a quasi-buried upper gate below the trench;
filling the trench with an insulator material to create a shallow trench isolation (STI) region, wherein the quasi-buried upper gate is disposed under a portion of the STI region such that the quasi-buried upper gate does not extend along a portion of the STI region proximate to the second side of the trench;
forming a lower gate region below the STI region;
forming a channel region disposed between the lower gate and the STI region;
forming a source region adjacent to the first side of the trench; and
forming a drain region adjacent to the second side of the trench.

### Claim 11 (depends on 10)

The method of claim 10, wherein the quasi-buried upper gate extends at least partially along the substantially vertical first side of the STI region.

### Claim 12 (depends on 10)

The method of claim 10, wherein the forming of the quasi-buried upper gate comprises ion implanting.

### Claim 13 (depends on 10)

The method of claim 10, further comprising forming an implantation layer in the channel region only under the source region, wherein the implantation layer includes a higher concentration of dopants than the channel region.

### Claim 14 (depends on 10)

The method of claim 10, further comprising forming a doped quasi-buried upper gate contact to the quasi-buried upper gate, wherein the quasi-buried upper gate contact has a higher concentration of dopants than the source region.

### Claim 15 (depends on 10)

The method of claim 10, wherein the quasi-buried upper gate has a dopant concentration in the range of approximately 1E18 to approximately 1E21 atom/cm3.

### Claim 16

A final design structure instantiated in a machine readable medium for designing and manufacturing a circuit, the final design structure comprising machine readable instructions for manufacturing at least one circuit and an integrated circuit, the circuit comprising: a junction field effect transistor (JFET) including:
a source region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the source region having an inner edge and an outer edge;
a drain region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the drain region having an inner edge and an outer edge;
a channel region disposed under the source region and the drain region; and
a shallow trench isolation (STI) region comprising an insulator material, the STI region having an upper surface substantially coplanar with the upper surface of the JFET, the STI region extending from the inner edge of the source region to the inner edge of the drain region.

### Claim 17 (depends on 16)

The final design structure of claim 16, the JFET further including a quasi-buried upper gate in the channel region, the quasi-buried gate positioned partially under the STI region, wherein the quasi-buried upper gate does not extend under a portion of the STI region proximate to the drain region.

### Claim 18 (depends on 16)

The final design structure of claim 16, wherein the final design structure comprises a netlist, which describes the circuit.

### Claim 19 (depends on 16)

The final design structure of claim 16, wherein the final design structure resides on a GDS storage medium.

### Claim 20 (depends on 16)

The final design structure of claim 16, wherein the final design structure includes test data files, characterization data, verification data, or design specifications.