# US 2012/0074386 A1 · Non-planar quantum well device having interfacial layer and method of forming same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2012/0074386 A1
- Document ID: US20120074386A1
- Status: Published application
- Kind: A1
- Application number: 12/924,307
- Filed: 2010-09-24
- Published: 2012-03-29
- Earliest claimed: 2010-09-24
- Assignees: Intel Corporation
- Inventors: Willy Rachmady; Ravi Pillarisetty; Van H. Le; Robert Chau
- Web page: https://patentgrep.com/patent/US20120074386A1

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/812: {Single quantum well structures}
- H10D 62/8161: {potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices (lateral superlattices, lateral surface superlattices H10D62/8181)}
- H10D 62/82: Heterojunctions
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 50/642: {Chemical etching}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

## Claims

### Claim 1

A method for forming a non-planar quantum well structure, comprising:
providing a quantum well structure having a substrate, a IV or III-V material barrier layer, and a quantum well layer;
selectively etching the quantum well structure to form a fin structure;
providing an interfacial layer over the fin structure, a material of the interfacial layer having a higher bandgap than a bandgap of a material of the fin structure;
providing a high-k dielectric layer over the interfacial layer; and
providing gate metal across the fin structure over the high-k dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the quantum well layer is a germanium quantum well layer, and the fin structure is a germanium fin structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein after depositing an interfacial layer over the fin structure and prior to depositing gate metal across the fin structure, the method further comprises providing an intermediate layer over the interfacial layer prior to providing the high-k dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the interfacial layer covers a 100 surface and a 110 surface of the fin structure.

### Claim 5 (depends on 1)

The method of claim 1, wherein the interfacial layer comprises silicon.

### Claim 6 (depends on 5)

The method of claim 5, wherein the interfacial layer comprises epitaxially grown silicon.

### Claim 7 (depends on 1)

The method of claim 1, wherein the interfacial layer comprises a single monolayer of atoms.

### Claim 8 (depends on 3)

The method of claim 3, wherein the intermediate layer comprises a dielectric material different from a material of the high-k layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the intermediate layer comprises at least one of silicon dioxide, alumina, zirconia and hafnium silicate.

### Claim 10 (depends on 3)

The method of claim 3, wherein providing the intermediate layer comprises oxidizing a surface of the interfacial layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein selectively etching the quantum well structure comprises:
patterning a hardmask on the quantum well structure for shallow trench isolation (STI) patterning;
etching an STI into the quantum well structure;
depositing a dielectric material into the STI; and
planarizing the dielectric material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dielectric material in the STI is recessed down to a bottom of the quantum well layer.

### Claim 13 (depends on 1)

The method of claim 1 further comprising forming drain and source regions at respective ends of the fin structure.

### Claim 14 (depends on 1)

The method of claim 1, wherein the quantum well structure further includes a doping layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the doping layer includes delta doping.

### Claim 16 (depends on 1)

The method of claim 1, wherein the quantum well layer is epitaxially grown.

### Claim 17

A non-planar quantum well device, comprising:
a quantum well structure having a substrate, a IV or III-V material barrier layer, and a quantum well layer;
a fin structure formed in the quantum well structure;
an interfacial layer provided over the fin structure;
a high-k layer provided over the interfacial layer; and
gate metal provided across the fin structure.

### Claim 18 (depends on 17)

The device of claim 17, wherein the quantum well layer is a germanium quantum well layer, and the fin structure is a germanium fin structure.

### Claim 19 (depends on 17)

The device of claim 17, further comprising an intermediate layer between the interfacial layer and the high-k dielectric layer.

### Claim 20 (depends on 17)

The device of claim 17, wherein the interfacial layer covers a 100 surface and a 110 surface of the fin structure.

### Claim 21 (depends on 17)

The device of claim 17, wherein the interfacial layer comprises silicon.

### Claim 22 (depends on 21)

The device of claim 21, wherein the interfacial layer comprises epitaxially grown silicon.

### Claim 23 (depends on 17)

The device of claim 17, wherein the interfacial layer comprises a single monolayer of atoms.

### Claim 24 (depends on 19)

The device of claim 19, wherein the intermediate layer comprises a dielectric material different from a material of the high-k layer.

### Claim 25 (depends on 24)

The device of claim 24, wherein the intermediate layer comprises at least one of silicon dioxide, alumina, zirconia and hafnium silicate.

### Claim 26 (depends on 19)

The device of claim 19, wherein the intermediate layer includes a material obtained from an oxidization of a surface of the interfacial layer.

### Claim 27 (depends on 17)

The device of claim 17, further including drain and source regions at respective ends of the fin structure.

### Claim 28 (depends on 17)

The device of claim 17, wherein the quantum well structure further includes a doping layer.

### Claim 29

A system comprising:
processor comprising:
a quantum well structure having a substrate, a IV or III-V material barrier layer, a doping layer, and a quantum well layer;
a fin structure formed in the quantum well structure;
an interfacial layer provided over the fin structure;
a high-k layer provided over the interfacial layer;
gate metal deposited across the fin structure over the high-k layer;
drain and source regions formed at respective ends of the fin structure; contact; and
a memory coupled to the processor.

### Claim 30 (depends on 29)

The system of claim 29, wherein the quantum well layer is a germanium quantum well layer, the fin structure is a germanium fin structure, the interfacial layer comprises epitaxially grown silicon, and the intermediate layer comprises silicon dioxide.