Design apparatus, method for having computer design semiconductor integrated circuit, and non-transitory computer-readable medium
AssigneeKabushiki Kaisha Toshiba
InventorNorifumi Kobayashi
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Abstract
According to one embodiment, a design apparatus includes an extractor, a regression equation generator and an output module. The extractor extracts a critical part from a net list of a semiconductor integrated circuit. The critical part has a delay value greater than a delay threshold. The regression equation generator generates a regression equation to reproduce the delay value of the critical part using a regression algorithm. The output module outputs the regression equation.
Claims20
A design apparatus comprising:
- an extractor configured to extract a critical part from a net list of a semiconductor integrated circuit, the critical part having a delay value greater than a delay threshold;
- a regression equation generator configured to generate a regression equation to reproduce the delay value of the critical part using a regression algorithm;
- and
- an output module configured to output the regression equation.
A method for having a computer design a semiconductor integrated circuit, the method comprising:
- extracting a critical part from a net list of the semiconductor integrated circuit, the critical part having a delay value greater than a delay threshold;
- generating a regression equation to reproduce the delay value of the critical part using a regression algorithm;
- and
- outputting the regression equation.
A non-transitory computer readable medium configured to store a program comprising instructions for:
- extracting a critical part from a net list of the semiconductor integrated circuit, the critical part having a delay value greater than a delay threshold;
- generating a regression equation to reproduce the delay value of the critical part using a regression algorithm;
- and
- outputting the regression equation.
Dependencies are inferred from the claim text.