Automated management of verification waivers
AssigneeInternational Business Machines Corporation
InventorGero Dittmann
Life of this patent
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Abstract
Automated management of verification waivers is disclosed. In one embodiment a method is provided comprising issuing a request to perform a verification run on a component of an electric circuit design, receiving configuration data specifying a list of waivers extracted from a plurality of waivers applicable to the electric circuit design as a whole where the list of waivers is extracted based on waiver validity period data and is applicable to the component rather than the electric circuit design as a whole. The described method further comprises identifying a potential design defect and generating a verification run result including a set of design defects of the component, the set including the potential design defect if no waiver of the list of waivers is determined to be applicable.
Claims16
A method comprising:
- issuing, via a design verification tool, a request to perform a verification run on a component of an electric circuit design;
- receiving, at said design verification tool and in response to an issuance of said request, configuration data specifying a list of waivers extracted from a plurality of waivers applicable to said electric circuit design as a whole, wherein
- said list of waivers is extracted based upon waiver validity period data specifying at least one of a waiver expiration date and a waiver grant date, and
- said list of waivers is applicable to said component of said electric circuit design rather than said electric circuit design as a whole;
- identifying, utilizing said design verification tool, a potential design defect of said component of said electric circuit design;
- and
- generating a verification run result including a set of design defects of said component of said electric circuit design, wherein
- said set of design defects includes said potential design defect in response to a determination that no waiver of said list of waivers is applicable to said potential design defect, and
- said set of design defects excludes said potential design defect in response to a determination that at least one waiver of said list of waivers is applicable to said potential design defect.
A circuit arrangement to verify an electronic circuit design utilizing a design verification tool, said circuit arrangement comprising:
- an entry tool;
- a control unit;
- a visualizing tool;
- and
- a database of defined waivers comprising a plurality of entries, each entry of said plurality of entries corresponding to a waiver and comprising a hardware component identifier and an associated defect type, wherein
- said design verification tool, during a verification run, ignores a found design defect in response to a determination that a corresponding waiver, defined to waive said found design defect, is present in said database of defined waivers, and
- each entry of said plurality of entries is further defined by metadata.
A computer program product for verifying an electronic circuit, the computer program product comprising:
- a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code, when executed by a computer, causes said computer to perform a method comprising,
- issuing a request to perform a verification run on a component of an electric circuit design;
- receiving, in response to an issuance of said request, configuration data specifying a list of waivers extracted from a plurality of waivers applicable to said electric circuit design as a whole, wherein
- said list of waivers is extracted based upon waiver validity period data specifying at least one of a waiver expiration date and a waiver grant date, and
- said list of waivers is applicable to said component of said electric circuit design rather than said electric circuit design as a whole;
- identifying a potential design defect of said component of said electric circuit design;
- and
- generating a verification run result including a set of design defects of said component of said electric circuit design, wherein
- said set of design defects includes said potential design defect in response to a determination that no waiver of said list of waivers is applicable to said potential design defect, and
- said set of design defects excludes said potential design defect in response to a determination that at least one waiver of said list of waivers is applicable to said potential design defect.
Dependencies are inferred from the claim text.