Layout verification apparatus and layout verification method

A layout verification apparatus of a semiconductor integrated circuit, the apparatus comprising:

• a design section configured to design a circuit diagram based on specification information;
• a layout creation section configured to create a layout of a semiconductor integrated circuit based on the circuit diagram;
• a first verification section configured to verify whether an element extracted from the layout of the semiconductor integrated circuit matches the circuit diagram;
• a second verification section configured to verify whether the layout of the semiconductor integrated circuit matches a design rule extracted from the specification information;
• and
• a filter processing section configured to apply a mask data used to a manufacture of the semiconductor integrated circuit to the verification target element which needs an ion implantation,
• wherein the filter processing section comprises a first logic section and a second logic section,
• the first logic section executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified, and
• the second logic section executes a logical exclusive OR between the verification target element before execution of the logical AND and the verification target element after execution of the logical AND.

A layout verification method of a semiconductor integrated circuit, the method comprising:

• designing a circuit diagram based on specification information;
• creating a layout of a semiconductor integrated circuit based on the circuit diagram;
• executing first verification to verify whether an element extracted from the layout of the semiconductor integrated circuit matches the circuit diagram;
• and
• executing second verification to verify whether the layout of the semiconductor integrated circuit matches a design rule extracted from the specification information,
• wherein one of the first and second verification includes a filter processing which applies a mask data used to a manufacture of the semiconductor integrated circuit to the verification target element which needs an ion implantation,
• wherein the filter processing executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified.

A layout verification method of a semiconductor integrated circuit, the method comprising:

• designing a circuit diagram based on specification information;
• creating a layout of a semiconductor integrated circuit based on the circuit diagram;
• verifying whether an element extracted from the layout of the semiconductor integrated circuit matches the circuit diagram;
• verifying whether the layout of the semiconductor integrated circuit matches a design rule extracted from the specification information;
• and
• applying, for a verification target element which needs an ion implantation, filter processing by mask data to be used to a manufacture of the semiconductor integrated circuit,
• wherein the filter processing comprises a first logic and a second logic,
• the first logic executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified, and
• the second logic executes a logical exclusive OR between the verification target element before execution of the logical AND and the verification target element after execution of the logical AND.