Method and apparatus for reducing x-pessimism in gate-level simulation and verification

A system, comprising:

• a processor;
• and
• a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the system to perform a method for reducing X-pessimism, the method comprising:
• identifying a set of reconvergent inputs of a combinational block in a gate-level design;
• and
• in response to determining that the combinational block is expected to exhibit X-pessimism during gate-level simulation, adding a correcting block to the gate-level design, wherein an output of the combinational block or the correcting block is selected based on the values of the set of reconvergent inputs.

A method for reducing X-pessimism, the method comprising:

• identifying a set of reconvergent inputs of a combinational block in a gate-level design;
• and
• in response to determining that the combinational block is expected to exhibit X-pessimism during gate-level simulation, modifying, by computer, the gate-level design, wherein said modifying includes:
• adding one or more replicas of the combinational block,
• adding one or more X-splitter blocks to couple each reconvergent input that is capable of having an indeterminate value to corresponding inputs of the one or more replicas, and
• adding one or more X-merger blocks to merge corresponding outputs from the replicas.