Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a memory including an array of memory cells. A buffer comprises latches to hold data from the memory cells. The latches constitute latch groups. The latches of each latch group are connected to corresponding one common line through a transfer circuit. An error corrector is connected to the common lines and detects an error bit in received data. A data transfer controller causes the buffer to read out data from memory cells to be verified, repeats reading out of all data in the latches in one latch group to corresponding one of common lines as to-be-verified data segment for different latch groups, and transfers the to-be-verified data segments to the error corrector. A verify controller causes the error corrector to determine whether an error bit is included in to-be-verified data includes the to-be-verified data segments.

Dependencies are inferred from the claim text.