Data read-out circuit in semiconductor memory device and method of data reading in semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorSatoru OKU
Life of this patent
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Abstract
A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.
Claims14
A semiconductor memory device comprising a data read-out circuit,
- said data read-out circuit comprising:
- a sense amplifier circuit configured to sense a data stored in a memory cell array by simultaneously comparing same stored data with a plurality of reference levels to simultaneously generate a plurality of read data based on said same stored data, and output said plurality of read data with regard to said same stored data;
- and
- a selector configured to select data corresponding to one of said simultaneously generated plurality of read data based on a control signal and output said selected data as an output data.
A semiconductor memory device comprising a data read-out circuit,
- said data read-out circuit comprising:
- a sense amplifier circuit configured to sense a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively, and output said plurality of read data with regard to said stored data;
- a selector configured to select a data corresponding to any one of said plurality of read data based on a control signal and output said selected data as an output data;
- and
- an error correction code (ECC) circuit configured to detect respective numbers of error bits in said plurality of read data by using an error correction code associated with said stored data,
- wherein said ECC circuit generates a plurality of error bit number signals indicating said detected respective numbers of error bits and outputs said plurality of error bit number signals as said control signal to said selector.
A semiconductor memory device comprising a data read-out circuit,
- said data read-out circuit comprising:
- a sense amplifier circuit configured to sense a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively, and output said plurality of read data with regard to said stored data;
- and
- a selector configured to select a data corresponding to any one of said plurality of read data based on a control signal and output said selected data as an output data,
- wherein said control signal is a mode signal indicating an operation mode of a semiconductor memory device provided with the data read-out circuit.
A semiconductor memory device comprising a correction circuit,
- said correction circuit comprising:
- an error correction code (ECC) circuit configured to receive a plurality of read data that are read out from a same memory cell group based on simultaneous comparison of data stored in said same memory cell group with a plurality of reference levels and detect respective numbers of error bits in said plurality of read data by using an error correction code associated with said data stored in said same memory cell group;
- and
- a selector configured to select a data corresponding to one of said plurality of read data having a minimum number of error bits.
A semiconductor memory device comprising:
- a data read-out circuit;
- and
- a data determination unit
- wherein said data read-out circuit comprises:
- a sense amplifier circuit configured to sense a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively, and output said plurality of read data with regard to said stored data;
- and
- a selector configured to select a data corresponding to any one of said plurality of read data based on a control signal and output said selected data as an output data,
- wherein if data determination by using one of said plurality of reference levels results in erroneous determination, said data determination unit makes the data determination by using another of said plurality of reference levels.
Dependencies are inferred from the claim text.