Memory controller with automatic error detection and correction

A memory system, comprising:

• a logical memory bank arranged to store and retrieve data, wherein the logical memory bank includes a plurality of memory lines of a predetermined data length, wherein each memory line includes a data portion, a corresponding valid bit, and a validation code;
• a validation code generator that is arranged to receive the data portion from a first memory line during a first read operation and to generate a new validation code in response to the received data portion;
• a validation code comparator that is arranged to compare the new validation code and the validation code of the first memory line and to produce a determination whether the validation code of the first memory line is valid;
• and
• a memory verification manager that is arranged to select the first memory line and, in response to an indication of an invalid code corresponding to the first memory line, to cause the new validation information to be loaded into a portion of the first memory line and to cause the corresponding valid bit to be set during a first write operation of the first memory line, wherein the memory manager reserves exclusive access of the logical memory bank, and wherein the first read operation of the first memory line occurs before a second read operation of a second memory line, wherein the second read operation occurs before the first write operation of the first memory line, wherein the first and second read operations and the first write operation occur during a period of time in which the memory verification manager has reserved exclusive access to the logical memory.

A memory verification manager, comprising:

• a validation code generator that is arranged to generate new validation information in response to the data portion of the first memory line;
• a validation code comparator that is arranged to determine whether an indication is received in response to the first read operation that the validation code associated with the first memory line is valid;
• and
• control logic that is arranged to reserve a block of exclusive accesses for the memory validation manager to exclusively access a logical memory bank, wherein the logical memory bank includes a plurality of memory lines of a predetermined data length, and wherein the block of exclusive accesses includes a first read operation of a first memory line in the logical memory bank, which is followed by a second read operation of a second memory line in the logical memory bank, which in turn is followed by a first write operation of the first memory line in the logical memory bank, which in turn is followed by a second write operation of the second memory line in the logical memory bank, wherein during the first write operation the first new validation code is associated with the first memory line and the first corresponding valid bit is set to valid.