Semiconductor memory device and controlling method

A controlling method for a semiconductor memory device that includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge, a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips, an error correction encoding unit, and a parameter processing unit,

• the controlling method comprising:
• generating, by the error correction encoding unit, a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips;
• and
• changing, by the parameter processing unit, the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and writing the parameters changed into the parameter storage units, respectively.