Non-volatile memory (nvm) with imminent error prediction

A method for determining an imminent failure of a non-volatile memory array, the method comprising:

• performing a first array integrity read operation of the non-volatile memory array until an error is detected;
• determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage;
• performing a second array integrity read operation of the non-volatile memory array, the second array integrity read operation comprising reading the array with a word line read voltage that is offset from the first threshold voltage and based on a predetermined width offset reference value;
• and
• checking a check sum value resulting from the second array integrity read operation, wherein when the check sum value is equal to a predetermined check sum value, there is not imminent failure in the memory array, and wherein when the check sum value is not equal to the predetermined check sum value, then there is imminent failure in the non-volatile memory array.

A system comprising:

• a memory array having a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and a bit line;
• a threshold voltage modulator coupled to the word line, the threshold voltage modulator for providing a range of voltage levels to the word line during a diagnostic mode of the system;
• an error correction code (ECC) decoder coupled to the memory array;
• and
• a memory controller coupled to the memory array, the threshold voltage modulator, and the ECC decoder, the memory controller for controlling a first array integrity read operation of the memory array until a read error is detected, the memory controller for determining that the read error is not ECC correctable, wherein a first word line voltage associated with the read error is characterized as being a first threshold voltage, the memory controller for controlling a second array integrity read operation of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage, and the memory controller for comparing a difference between the first and second threshold voltages to a predetermined value.