Back to results
US 2012/0072793 A1Published application
Registers with Full Scan Capability
AssigneeQUALCOMM Incorporated
InventorsHari M. Rao, Sei Seung Yoon, Nan Chen
Life of this patent
Estimating the term…
Abstract
A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
Claims35
A scannable register comprising:
- a plurality of storage cells, each storage cell having:
- a scan input and a scan output,
- a latch coupled to the scan input, the latch having a latch output, and a switch gate, coupled to the latch output, having a switch control input to receive a scan clock and, in response to the scan clock, to switchably couple the latch output to the scan output and to uncouple the latch output from the scan output, wherein
- the scan output of each of the storage cells is coupled to the scan input of a corresponding next one of the storage cells.
1 more element
A method for scan test of a first latch having an input and an output and a second latch having an input and an output, comprising steps of:
- coupling a given scan data to the input of the first latch, to switch the first latch to switch to a state corresponding to said given scan data;
- uncoupling said given scan data from the input of the first latch to latch the first latch at said state;
- coupling the output of the first latch while latched at said state to the input of the second latch to switch the second latch to said state;
- and
- uncoupling the output of the first latch from the input of the second latch to latch the second latch at said state.
2 more elements
A method for scan test, comprising:
- a) providing approximately N/2 odd storage cells and approximately N/2 even scannable storage cells, each of the storage cells having a latch having a latch input and latch output, the latch output of each odd storage cell being selectively coupled to the latch input of a corresponding next even storage cell, and the latch output of each even storage cell being selectively coupled to the latch input of a corresponding next odd storage cell;
- b) generating a scan clock having repeating cycles, each cycle having a first clock event followed by a second clock event;
- c) in response to the first clock event of a scan clock cycle, coupling the latch output of each of the odd storage cells to the latch input of its corresponding next even storage cell to switch the state of the latch of its corresponding next even storage cell to the state of the latch of the odd storage cell and, substantially concurrent with said coupling, uncoupling the latch output of each of the even storage cells from the latch input of its corresponding next odd storage cell to latch the state of the latch of said odd s storage cell at the state of said latch prior to said uncoupling;
- d) in response to the second clock event of said scan clock cycle, uncoupling the latch output of each of the even storage cells from the latch input of its corresponding next odd storage cell to latch the state of the latch of its corresponding next odd storage cell to the state of the latch of the even storage cell and, substantially concurrent with said uncoupling, coupling the latch output of each of the odd storage cells to the latch input of its corresponding next even storage cell to switch the state of the latch of said even storage cell to the state of the latch of the odd storage cell.
1 more element
A scannable register having a first latch having a latch input and a latch output and a second latch having a latch input and a latch output, comprising:
- means for coupling a given scan data to the input of the first latch to switch the first latch to a state corresponding to said given scan data, and for uncoupling said given scan data from the input of the first latch to latch the first latch at said state;
- and
- means for coupling the output of the first latch while latched at said state to the input of the second latch to switch the second latch to said state, and for uncoupling the output of the first latch from the second latch, while said second latch is latched to said state, to latch the second latch at said state.
A scannable N-bit register, comprising:
- N one-bit storage cells, each of the storage cells having a one-bit latch having a latch input and a latch output, arranged as approximately N/2 even storage cells and approximately N/2 odd storage cells, each even storage cell having one corresponding next odd storage cell from among said odd storage cells and each odd storage cell having a corresponding one next even storage cell from among said even storage cells;
- means for generating a scan clock having repeating cycles, each cycle having a first clock event followed by a second clock event;
- first shift means for receiving the scan clock and, in response to the first clock event of a scan clock cycle, coupling the latch output of each of the odd storage cells to the latch input of its corresponding next even storage cell to switch the state of the latch of its corresponding next even storage cell to the state of the latch of the odd storage cell and, substantially concurrent with said coupling, uncoupling the latch output of each of the even storage cells from the latch input of its corresponding next odd storage cell to latch the state of the latch of said odd storage cell at the state of said latch prior to said uncoupling;
- and
- second shift means for receiving said scan clock and, in response to the second clock event of said scan clock cycle, uncoupling the latch output of each of the even storage cells from the latch input of its corresponding next odd storage cell to latch the state of the latch of its corresponding next odd storage cell to the state of the latch of the even storage cell and, substantially concurrent with said uncoupling, coupling the latch output of each of the odd storage cells to the latch input of its corresponding next even storage cell to switch the state of the latch of said even storage cell to the state of the latch of said odd storage cell.
2 more elements
Dependencies are inferred from the claim text.