Integrated circuit with memory built-in self test (mbist) circuitry having enhanced features and methods

An integrated circuit (IC) comprising:

• a plurality of functional units, each including multiple arrays of memory elements;
• memory built-in self test (MBIST) circuitry associated with a plurality of arrays of each of the functional units;
• the MBIST circuitry configured to conduct serial testing of the plurality of arrays of each functional unit;
• and
• the MBIST circuitry configured to conduct parallel initialization of the plurality of arrays of the plurality of functional units by providing initialization data to the plurality of arrays of the plurality of functional units in parallel.

An integrated circuit (IC) comprising:

• a functional unit including multiple arrays of memory elements;
• memory built-in self test (MBIST) circuitry associated with a plurality of arrays of the functional unit;
• and
• the MBIST circuitry configured to conduct serial testing of the plurality of arrays and to conduct parallel initialization of the plurality of arrays by providing initialization data to the plurality of arrays in parallel to set the memory elements to an initialization state.