Bit error rate checker receiving serial data signal from an eye viewer

An integrated circuit (IC) comprising:

• a clock data recovery (CDR) circuitry;
• an eye viewer coupled to the CDR circuitry;
• a deserializer coupled to the CDR circuitry and the eye viewer;
• an IC core coupled to the deserializer;
• and
• a bit error rate (BER) checker coupled to the eye viewer, the CDR circuitry, and the IC core, wherein the BER checker comprises:
• a comparator;
• a programmable delay circuit coupled to the comparator;
• and
• an error counter coupled to the comparator;
• wherein the BER checker is outside the IC core.

A method of bit error rate (BER) checking, the method comprising:

• sampling a data signal to provide a sampled serial data signal;
• selecting between a recovered serial data signal and a known data signal to provide a selected reference serial data signal;
• receiving the sampled serial data signal and the selected reference serial data signal;
• and
• comparing the sampled serial data signal and the selected reference serial data signal to provide a BER of the sampled serial data signal;
• wherein the sampling, selecting, receiving, and comparing are performed in an integrated circuit (IC).